📄 mcf537x_ssi.h
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/* * File: mcf537x_ssi.h * Purpose: Register and bit definitions */#ifndef __MCF537X_SSI_H__#define __MCF537X_SSI_H__/*********************************************************************** Synchronous Serial Interface (SSI)**********************************************************************//* Register read/write macros */#define MCF_SSI_TX0 (*(vuint32*)(0xFC0BC000))#define MCF_SSI_TX1 (*(vuint32*)(0xFC0BC004))#define MCF_SSI_RX0 (*(vuint32*)(0xFC0BC008))#define MCF_SSI_RX1 (*(vuint32*)(0xFC0BC00C))#define MCF_SSI_CR (*(vuint32*)(0xFC0BC010))#define MCF_SSI_ISR (*(vuint32*)(0xFC0BC014))#define MCF_SSI_IER (*(vuint32*)(0xFC0BC018))#define MCF_SSI_TCR (*(vuint32*)(0xFC0BC01C))#define MCF_SSI_RCR (*(vuint32*)(0xFC0BC020))#define MCF_SSI_CCR (*(vuint32*)(0xFC0BC024))#define MCF_SSI_FCSR (*(vuint32*)(0xFC0BC02C))#define MCF_SSI_ACR (*(vuint32*)(0xFC0BC038))#define MCF_SSI_ACADD (*(vuint32*)(0xFC0BC03C))#define MCF_SSI_ACDAT (*(vuint32*)(0xFC0BC040))#define MCF_SSI_ATAG (*(vuint32*)(0xFC0BC044))#define MCF_SSI_TMASK (*(vuint32*)(0xFC0BC048))#define MCF_SSI_RMASK (*(vuint32*)(0xFC0BC04C))/* Bit definitions and macros for MCF_SSI_TX */#define MCF_SSI_TX_SSI_TX(x) (((x)&0xFFFFFFFF)<<0)/* Bit definitions and macros for MCF_SSI_RX */#define MCF_SSI_RX_SSI_RX(x) (((x)&0xFFFFFFFF)<<0)/* Bit definitions and macros for MCF_SSI_CR */#define MCF_SSI_CR_SSI_EN (0x00000001)#define MCF_SSI_CR_TE (0x00000002)#define MCF_SSI_CR_RE (0x00000004)#define MCF_SSI_CR_NET (0x00000008)#define MCF_SSI_CR_SYN (0x00000010)#define MCF_SSI_CR_I2S(x) (((x)&0x00000003)<<5)#define MCF_SSI_CR_MCE (0x00000080)#define MCF_SSI_CR_TCH (0x00000100)#define MCF_SSI_CR_CIS (0x00000200)#define MCF_SSI_CR_I2S_NORMAL (0x00000000)#define MCF_SSI_CR_I2S_MASTER (0x00000020)#define MCF_SSI_CR_I2S_SLAVE (0x00000040)/* Bit definitions and macros for MCF_SSI_ISR */#define MCF_SSI_ISR_TFE0 (0x00000001)#define MCF_SSI_ISR_TFE1 (0x00000002)#define MCF_SSI_ISR_RFF0 (0x00000004)#define MCF_SSI_ISR_RFF1 (0x00000008)#define MCF_SSI_ISR_RLS (0x00000010)#define MCF_SSI_ISR_TLS (0x00000020)#define MCF_SSI_ISR_RFS (0x00000040)#define MCF_SSI_ISR_TFS (0x00000080)#define MCF_SSI_ISR_TUE0 (0x00000100)#define MCF_SSI_ISR_TUE1 (0x00000200)#define MCF_SSI_ISR_ROE0 (0x00000400)#define MCF_SSI_ISR_ROE1 (0x00000800)#define MCF_SSI_ISR_TDE0 (0x00001000)#define MCF_SSI_ISR_TDE1 (0x00002000)#define MCF_SSI_ISR_RDR0 (0x00004000)#define MCF_SSI_ISR_RDR1 (0x00008000)#define MCF_SSI_ISR_RXT (0x00010000)#define MCF_SSI_ISR_CMDDU (0x00020000)#define MCF_SSI_ISR_CMDAU (0x00040000)/* Bit definitions and macros for MCF_SSI_IER */#define MCF_SSI_IER_TFE0 (0x00000001)#define MCF_SSI_IER_TFE1 (0x00000002)#define MCF_SSI_IER_RFF0 (0x00000004)#define MCF_SSI_IER_RFF1 (0x00000008)#define MCF_SSI_IER_RLS (0x00000010)#define MCF_SSI_IER_TLS (0x00000020)#define MCF_SSI_IER_RFS (0x00000040)#define MCF_SSI_IER_TFS (0x00000080)#define MCF_SSI_IER_TUE0 (0x00000100)#define MCF_SSI_IER_TUE1 (0x00000200)#define MCF_SSI_IER_ROE0 (0x00000400)#define MCF_SSI_IER_ROE1 (0x00000800)#define MCF_SSI_IER_TDE0 (0x00001000)#define MCF_SSI_IER_TDE1 (0x00002000)#define MCF_SSI_IER_RDR0 (0x00004000)#define MCF_SSI_IER_RDR1 (0x00008000)#define MCF_SSI_IER_RXT (0x00010000)#define MCF_SSI_IER_CMDU (0x00020000)#define MCF_SSI_IER_CMDAU (0x00040000)#define MCF_SSI_IER_TIE (0x00080000)#define MCF_SSI_IER_TDMAE (0x00100000)#define MCF_SSI_IER_RIE (0x00200000)#define MCF_SSI_IER_RDMAE (0x00400000)/* Bit definitions and macros for MCF_SSI_TCR */#define MCF_SSI_TCR_TEFS (0x00000001)#define MCF_SSI_TCR_TFSL (0x00000002)#define MCF_SSI_TCR_TFSI (0x00000004)#define MCF_SSI_TCR_TSCKP (0x00000008)#define MCF_SSI_TCR_TSHFD (0x00000010)#define MCF_SSI_TCR_TXDIR (0x00000020)#define MCF_SSI_TCR_TFDIR (0x00000040)#define MCF_SSI_TCR_TFEN0 (0x00000080)#define MCF_SSI_TCR_TFEN1 (0x00000100)#define MCF_SSI_TCR_TXBIT0 (0x00000200)/* Bit definitions and macros for MCF_SSI_RCR */#define MCF_SSI_RCR_REFS (0x00000001)#define MCF_SSI_RCR_RFSL (0x00000002)#define MCF_SSI_RCR_RFSI (0x00000004)#define MCF_SSI_RCR_RSCKP (0x00000008)#define MCF_SSI_RCR_RSHFD (0x00000010)#define MCF_SSI_RCR_RFEN0 (0x00000080)#define MCF_SSI_RCR_RFEN1 (0x00000100)#define MCF_SSI_RCR_RXBIT0 (0x00000200)#define MCF_SSI_RCR_RXEXT (0x00000400)/* Bit definitions and macros for MCF_SSI_CCR */#define MCF_SSI_CCR_PM(x) (((x)&0x000000FF)<<0)#define MCF_SSI_CCR_DC(x) (((x)&0x0000001F)<<8)#define MCF_SSI_CCR_WL(x) (((x)&0x0000000F)<<13)#define MCF_SSI_CCR_PSR (0x00020000)#define MCF_SSI_CCR_DIV2 (0x00040000)/* Bit definitions and macros for MCF_SSI_FCSR */#define MCF_SSI_FCSR_TFWM0(x) (((x)&0x0000000F)<<0)#define MCF_SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)#define MCF_SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)#define MCF_SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)#define MCF_SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)#define MCF_SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)#define MCF_SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)#define MCF_SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)/* Bit definitions and macros for MCF_SSI_ACR */#define MCF_SSI_ACR_AC97EN (0x00000001)#define MCF_SSI_ACR_FV (0x00000002)#define MCF_SSI_ACR_TIF (0x00000004)#define MCF_SSI_ACR_RD (0x00000008)#define MCF_SSI_ACR_WR (0x00000010)#define MCF_SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)/* Bit definitions and macros for MCF_SSI_ACADD */#define MCF_SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF)<<0)/* Bit definitions and macros for MCF_SSI_ACDAT */#define MCF_SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF)<<0)/* Bit definitions and macros for MCF_SSI_ATAG */#define MCF_SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF)<<0)/* Bit definitions and macros for MCF_SSI_TMASK */#define MCF_SSI_TMASK_SSI_TMASK(x) (((x)&0xFFFFFFFF)<<0)/* Bit definitions and macros for MCF_SSI_RMASK */#define MCF_SSI_RMASK_SSI_RMASK(x) (((x)&0xFFFFFFFF)<<0)/********************************************************************/#endif /* __MCF537X_SSI_H__ */⌨️ 快捷键说明
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