📄 davincievm_arm.gel.txt
字号:
pll2_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 );
DDR2_freq = pll2_freq / ( 2 * ( ( *pll_div2 & 0x1f ) + 1 ) );
vpss_freq = pll2_freq / ( ( *pll_div1 & 0x1f ) + 1 );
GEL_TextOut( "(VPSS = %d MHz + ",,,,, vpss_freq );
GEL_TextOut( "DDR2 Phy = %d MHz + ",,,,, DDR2_freq );
if ( clock_source == 0 )
GEL_TextOut( "Onchip Oscillator)... " );
else
GEL_TextOut( "External Clock)... " );
GEL_TextOut( "[Done]\n" );
}
hotmenu
Setup_PLL2_DDR_135_MHz_OscIn( )
{
/* [VPSS @54 MHz][DDR @135 MHz] w/ Onchip Oscillator */
setup_pll_2( 0, 19, 9, 1 );
}
hotmenu
Setup_PLL2_DDR_162_MHz_OscIn( )
{
/* [VPSS @54 MHz][DDR @162 MHz] w/ Onchip Oscillator */
setup_pll_2( 0, 23, 11, 1 );
}
/* ------------------------------------------------------------------------ *
* *
* setup_DDR2( ) *
* Configure DDR2 to run at specified frequency. *
* *
* ------------------------------------------------------------------------ */
setup_DDR2( int freq )
{
#define DDR_SDBCR *( unsigned int* )( 0x20000008 )
#define DDR_SDRCR *( unsigned int* )( 0x2000000c )
#define DDR_SDTIMR *( unsigned int* )( 0x20000010 )
#define DDR_SDTIMR2 *( unsigned int* )( 0x20000014 )
#define DDR_DDRPHYCR *( unsigned int* )( 0x200000e4 )
#define DDR_VTPIOCR *( unsigned int* )( 0x200000f0 )
#define DDR_DDRVTPR *( unsigned int* )( 0x01c42030 )
#define DDR_DDRVTPER *( unsigned int* )( 0x01c4004c )
int dummy_read;
int pch_nch;
GEL_TextOut( "Setup DDR2 (%d MHz + 32-bit bus)... ",,,,, freq );
/*
* Step 1 - Setup PLL2
* Step 2 - Enable DDR2 PHY
*/
psc_change_state( 13, 3 );
/*
* Step 3 - DDR2 Initialization
*/
DDR_DDRPHYCR = 0x50006405; // DLL powered, ReadLatency=6
DDR_SDBCR = 0x00138632; // DDR Bank: 32-bit bus, CAS=3,
// 8 banks, 1024-word pg
if ( freq == 135 )
{
DDR_SDTIMR = 0x20922991; // DDR Timing
DDR_SDTIMR2 = 0x0012c722; // DDR Timing
}
else /* Default to 162 MHz */
{
DDR_SDTIMR = 0x28923209; // DDR Timing
DDR_SDTIMR2 = 0x0016c722; // DDR Timing
}
DDR_SDBCR = 0x00130632; // DDR Bank: cannot modify
DDR_SDRCR = freq * 7.8; // Refresh Control [ 7.8 usec * freq ]
/*
* Step 4 - Dummy Read from DDR2
*/
dummy_read = *( int* )0x80000000;
/*
* Step 5 - Soft Reset ( SYNCRESET followed by ENABLE ) of DDR2 PHY
*/
psc_change_state( 13, 1 );
psc_change_state( 13, 3 );
/*
* Step 6 - Enable VTP calibration
* Step 7 - Wait for VTP calibration ( 33 VTP cycles )
*/
DDR_VTPIOCR = 0x201f;
DDR_VTPIOCR = 0xa01f;
_wait( 1500 );
/*
* Step 8 - Enable access to DDR VTP reg
* Step 9 - Reat P & N channels
* Step 10 - Set VTP fields PCH & NCH
*/
DDR_DDRVTPER = 1;
pch_nch = DDR_DDRVTPR & 0x3ff;
DDR_VTPIOCR = 0xa000 | pch_nch;
/*
* Step 11 - Disable VTP calibaration
* - Disable access to DDR VTP register
*/
DDR_VTPIOCR &= ~0x2000;
DDR_DDRVTPER = 0;
GEL_TextOut( "[Done]\n" );
}
hotmenu
Setup_DDR_135_MHz( )
{
setup_DDR2( 135 );
}
hotmenu
Setup_DDR_162_MHz( )
{
setup_DDR2( 162 );
}
/* ------------------------------------------------------------------------ *
* *
* setup_aemif( ) *
* Setup Async-EMIF to Max Wait cycles and specified bus width. *
* *
* ------------------------------------------------------------------------ */
setup_aemif( int bus_width )
{
#define AEMIF_BASE 0x01e00000
#define AWCCR *( unsigned int* )( 0x01e00004 )
#define A1CR *( unsigned int* )( 0x01e00010 )
#define A2CR *( unsigned int* )( 0x01e00014 )
#define A3CR *( unsigned int* )( 0x01e00018 )
#define A4CR *( unsigned int* )( 0x01e0001c )
#define NANDFCR *( unsigned int* )( 0x01e00060 )
GEL_TextOut( "Setup Asyn Emif (%d-bit bus)... ",,,,, bus_width );
AWCCR = 0x00000000; // No extended wait cycles
if ( bus_width == 8 ) // Setup for 8-bit bus
{
A1CR = 0x3ffffffc; // Wait cycles - Max Wait
A2CR = 0x3ffffffc;
A3CR = 0x3ffffffc;
A4CR = 0x3ffffffc;
}
if ( bus_width == 16 ) // Setup for 16-bit bus
{
A1CR = 0x3ffffffd; // Wait cycles - Max Wait
A2CR = 0x3ffffffd;
A3CR = 0x3ffffffd;
A4CR = 0x3ffffffd;
}
NANDFCR = 0x00000000; // NAND controller not used
GEL_TextOut( "[Done]\n" );
}
/*hotmenu*/
Reset_EMIF_8Bit_Bus( )
{
setup_aemif( 8 );
}
/*hotmenu*/
Reset_EMIF_16Bit_Bus( )
{
setup_aemif( 16 );
}
/* ------------------------------------------------------------------------ *
* *
* Setup_EMIF_CS2( ) *
* Setup Async-EMIF to depending on the memory device. *
* *
* ------------------------------------------------------------------------ */
hotmenu
Setup_EMIF_CS2_NorFlash_16Bit( )
{
#define AEMIF_BASE 0x01e00000
#define AEMIF_A1CR *( unsigned int* )( 0x01e00010 )
#define AEMIF_NANDFCR *( unsigned int* )( 0x01e00060 )
#define EMIF_CS2_PTR *( unsigned int* )( 0x02000000 )
GEL_TextOut( "Setup EMIF CS2 - NOR Flash (16-bit bus)... " );
AEMIF_A1CR = 0x0050043d; // NOR Flash settings ( @ 99MHz or below )
AEMIF_NANDFCR &= 0xfffffffe; // Disable Hw NAND Flash controller
EMIF_CS2_PTR = 0xf0; // Reset Flash memory to Read mode
GEL_TextOut( "[Done]\n" );
}
hotmenu
Setup_EMIF_CS2_SRAM_16Bit( )
{
#define AEMIF_BASE 0x01e00000
#define AEMIF_A1CR *( unsigned int* )( 0x01e00010 )
#define AEMIF_NANDFCR *( unsigned int* )( 0x01e00060 )
#define EMIF_CS2_BASE ( 0x02000000 )
GEL_TextOut( "Setup EMIF CS2 - SRAM (16-bit bus)... " );
AEMIF_A1CR = 0x00900305; // SRAM settings ( @ 99MHz or below )
AEMIF_NANDFCR &= 0xfffffffe; // Disable Hw NAND Flash controller
GEL_TextOut( "[Done]\n" );
}
hotmenu
Setup_EMIF_CS2_NandFlash_8Bit( )
{
#define AEMIF_BASE 0x01e00000
#define AEMIF_A1CR *( unsigned int* )( 0x01e00010 )
#define AEMIF_NANDFCR *( unsigned int* )( 0x01e00060 )
#define NAND_CLE_PTR *( unsigned char* )( 0x02000010 )
GEL_TextOut( "Setup EMIF CS2 - NAND Flash (8-bit bus)... " );
AEMIF_A1CR = 0x04422318; // NAND Flash settings ( @ 99MHz or below )
AEMIF_NANDFCR |= 0x00000001; // Enable Hw NAND Flash controller
NAND_CLE_PTR = 0xff; // Reset Flash memory to Read Mode
GEL_TextOut( "[Done]\n" );
}
menuitem "DaVinci EVM Boot Mode";
/* ------------------------------------------------------------------------ *
* *
* Boot_Mode_Reader( ) *
* Read and Print boot mode *
* *
* ------------------------------------------------------------------------ */
hotmenu
Boot_Mode_Reader( )
{
#define BOOTCFG *( unsigned int* )( 0x01c40014 )
int dsp_boot = ( BOOTCFG >> 8 ) & 0x1;
int boot_mode = ( BOOTCFG >> 6 ) & 0x3;
int em_width = ( BOOTCFG >> 5 ) & 0x1;
int aeaw = ( BOOTCFG >> 0 ) & 0x1f;
GEL_TextOut( "\nBoot Mode Reader:\n" );
if ( boot_mode == 0 )
GEL_TextOut( " > [Boot Mode]: NAND Boot\n" );
else if ( boot_mode == 1 )
GEL_TextOut( " > [Boot Mode]: NOR Boot\n" );
else if ( boot_mode == 3 )
GEL_TextOut( " > [Boot Mode]: UART0 Boot\n" );
else
GEL_TextOut( " >>>>>> ERROR boot option not supported <<<<<<\n" );
if ( em_width == 0 )
GEL_TextOut( " > [Bus Width]: 8-bit\n" );
if ( em_width == 1 )
GEL_TextOut( " > [Bus Width]: 16-bit\n" );
if ( dsp_boot == 0 )
GEL_TextOut( " > [DSP Boot] : ARM boots C64x+\n" );
if ( dsp_boot == 1 )
GEL_TextOut( " > [DSP Boot] : C64x+ self boots\n" );
GEL_TextOut( " > [AEAW] : %x\n",,,,, aeaw );
GEL_TextOut( "\n" );
}
menuitem "DaVinci EVM DSP";
/* ------------------------------------------------------------------------ *
* *
* boot_dsp_from_arm( ) *
* Boot DSP from ARM side. *
* *
* ------------------------------------------------------------------------ */
boot_dsp_from_arm( unsigned int boot_aDDRess )
{
#define DSPBOOTADDR *( unsigned int* )( 0x01c40008 )
#define PSC_MDCTL_DSP *( unsigned int* )( 0x01c41a00 + ( 4 * 39 ) )
GEL_TextOut( "Boot DSP from %x ... ",,,,, boot_aDDRess );
/*
* Step 1 - Turn DSP power on
*/
psc_change_state( 39, 3 );
psc_change_state( 40, 3 );
/*
* Step 2 - Assert local reset
*/
PSC_MDCTL_DSP &= 0xfeff;
/*
* Step 3 - Program DSP boot aDDRess
* - Fill in memory w/ branch to self opcode
*/
DSPBOOTADDR = boot_aDDRess;
GEL_MemoryFill( boot_aDDRess, 0, 32, 0x13 );
/*
* 4. Release from reset
*/
PSC_MDCTL_DSP |= 0x0100;
GEL_TextOut( "[Done]\n" );
}
hotmenu
DSP_Boot_from_L2_Sram( )
{
boot_dsp_from_arm( 0x11800000 ); // L2 SRAM Memory
}
hotmenu
DSP_Boot_from_DDR2( )
{
boot_dsp_from_arm( 0x80000000 ); // DDR2 Memory
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -