davincievm_arm.gel.txt

TI公司DaVinci系列DSP评估板的原理图

 *                                                                          *
 * ------------------------------------------------------------------------ */
psc_change_state( int id, int state )
{
    #define PSC_PTCMD           *( unsigned int* )( 0x01c41120 )
    #define PSC_PTSTAT          *( unsigned int* )( 0x01c41128 )
    unsigned int* mdstat        = ( unsigned int* )( 0x01c41800 + ( 4 * id ) );
    unsigned int* mdctl         = ( unsigned int* )( 0x01c41a00 + ( 4 * id ) );
    int set_interrupt;

    /*
     *  Step 0 - Ignore request if the state is already set as is
     */
    if ( ( *mdstat & 0x1f ) == state )
        return;

    /*
     *  Step 0 - Enable the DSP & IMCOP seperately
     */
    if ( ( id == 39 ) || ( id == 40 ) )
    {
        psc_turn_on_dsp_power_domain( );
        return;
    }

    /*
     *  Step 1 - Wait for PTSTAT.GOSTAT to clear
     */
    while( PSC_PTSTAT & 1 );

    /*
     *  Step 2 - Set MDCTLx.NEXT to new state
     */
    *mdctl &= ~0x1f;
    *mdctl |= state;

    /*
     *  Step 2.5 - Enable interrutps if it is needed
     */
    set_interrupt = psc_use_interrupt( id );
    if ( set_interrupt )
        *mdctl |= 0x0200;

    /*
     *  Step 3 - Start power transition ( set PTCMD.GO to 1 )
     */
    PSC_PTCMD = 1;

    /*
     *  Step 4 - Wait for PTSTAT.GOSTAT to clear
     */
    while( PSC_PTSTAT & 1 );

    /*
     *  Step 5 - Verify state changed
     */
    while( ( *mdstat & 0x1f ) != state );

    /*
     *  Step 6 - Clear Interrupt
     */
    if ( set_interrupt )
       *mdctl &= ~0x0200;
}

_wait( int delay )
{
    int i;
    for( i = 0 ; i < delay ; i++ ){}
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  setup_pll_1( )                                                          *
 *                                                                          *
 *      clock_source    <- 0: Onchip Oscillator                             *
 *                         1: External Clock                                *
 *                                                                          *
 *      pll_mult        <- 21: 22x Multiplier * 27MHz Clk = 594 MHz         *
 *                         16: 17x Multiplier * 27MHz Clk = 459 MHz         *
 *                                                                          *
 * ------------------------------------------------------------------------ */
setup_pll_1( int clock_source, int pll_mult )
{
    unsigned int* pll_ctl           = ( unsigned int* )( 0x01c40900 );
    unsigned int* pll_pllm          = ( unsigned int* )( 0x01c40910 );
    unsigned int* pll_postdiv       = ( unsigned int* )( 0x01c40928 );
    unsigned int* pll_bpdiv         = ( unsigned int* )( 0x01c4092c );

    int pll1_freq = 27 * ( pll_mult + 1 );
    int dsp_freq = pll1_freq;
    int arm_freq = pll1_freq / 2;
    int postdiv = 0;
    int bypass_div = 0;

    GEL_TextOut( "Setup PLL1 " );

    /*
     *  Step 0 - Ignore request if the PLL is already set as is
     */
    if ( ( ( *pll_ctl & 0x0100 ) >> 8 ) == clock_source )
    {
        if ( ( *pll_pllm & 0x3f ) == ( pll_mult & 0x3f ) )
        {
            if ( ( *pll_postdiv & 0x1f ) == ( postdiv & 0x1f ) )
            {
                GEL_TextOut( "(DSP = %d MHz + ",,,,, dsp_freq );
                GEL_TextOut( "ARM = %d MHz + ",,,,, arm_freq );
                if ( clock_source == 0 )
                    GEL_TextOut( "Onchip Oscillator)... " );
                else
                    GEL_TextOut( "External Clock)... " );
                GEL_TextOut( "[Already Set]\n" );
                return;
            }
        }
    }
    /*
     *  Step 1 - Set clock mode
     */
    if ( clock_source == 0 )
        *pll_ctl &= ~0x0100;    // Onchip Oscillator
    else
        *pll_ctl |= 0x0100;     // External Clock

    /*
     *  Step 2 - Set PLL to bypass
     *         - Wait for PLL to stabilize
     */
    *pll_ctl &= ~0x0021;
    _wait( 150 );

    /*
     *  Step 3 - Reset PLL
     */
    *pll_ctl &= ~0x0008;

    /*
     *  Step 4 - Disable PLL
     *  Step 5 - Powerup PLL
     *  Step 6 - Enable PLL
     *  Step 7 - Wait for PLL to stabilize
     */
    *pll_ctl |= 0x0010;         // Disable PLL
    *pll_ctl &= ~0x0002;        // Power up PLL
    *pll_ctl &= ~0x0010;        // Enable PLL
    _wait( 150 );               // Wait for PLL to stabilize

    /*
     *  Step 8 - Load PLL multiplier
     */
    *pll_pllm = pll_mult & 0x3f;

    /*
     *  Step 9 - Set PLL post dividers
     *           For PLL1: DSP, ARM, VPSS, VICP, & Per. dividers are all fixed
     */
    *pll_bpdiv = 0x8000 | bypass_div;   // Bypass divider
    *pll_postdiv = 0x8000 | postdiv;    // Post divider

    /*
     *  Step 10 - Wait for PLL to reset ( 2000 cycles )
     *  Step 11 - Release from reset
     */
    _wait( 2000 );
    *pll_ctl |= 0x0008;

    /*
     *  Step 12 - Wait for PLL to re-lock ( 2000 cycles )
     *  Step 13 - Switch out of BYPASS mode
     */
    _wait( 2000 );
    *pll_ctl |= 0x0001;

    pll1_freq = 27 * ( ( *pll_pllm & 0x3f ) + 1 );
    dsp_freq = pll1_freq;
    arm_freq = pll1_freq / 2;

    GEL_TextOut( "(DSP = %d MHz + ",,,,, dsp_freq );
    GEL_TextOut( "ARM = %d MHz + ",,,,, arm_freq );

    if ( clock_source == 0 )
        GEL_TextOut( "Onchip Oscillator)... " );
    else
        GEL_TextOut( "External Clock)... " );

    GEL_TextOut( "[Done]\n" );
}

hotmenu
Setup_PLL1_459_MHz_OscIn( )
{
    setup_pll_1( 0, 16 );   // DSP @ 459 MHz & ARM @ 229.5 MHz w/ Onchip Oscillator
}
hotmenu
Setup_PLL1_594_MHz_OscIn( )
{
    setup_pll_1( 0, 21 );   // DSP @ 594 MHz & ARM @ 297 MHz w/ Onchip Oscillator
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  setup_pll_2( )                                                          *
 *                                                                          *
 *      clock_source    <- 0: Onchip Oscillator                             *
 *                         1: External Clock                                *
 *                                                                          *
 *      pll_mult        <- PLL Multiplier                                   *
 *                         23: 24x Multiplier * 27MHz Clk = 648 MHz         *
 *                                                                          *
 *      vpss_div        <- VPSS divider ( For PLL2 )                        *
 *                         11: 648 MHz Clk / 12x Divider = 54 MHz           *
 *                                                                          *
 *      DDR2_div        <- DDR2 divider ( For PLL2 )                        *
 *                         1: 648 MHz Clk / (2*2)x Divider = 162 MHz        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
setup_pll_2( int clock_source, int pll_mult, int vpss_div, int DDR2_div )
{
    unsigned int* pll_ctl       = ( unsigned int* )( 0x01c40d00 );
    unsigned int* pll_pllm      = ( unsigned int* )( 0x01c40d10 );
    unsigned int* pll_cmd       = ( unsigned int* )( 0x01c40d38 );
    unsigned int* pll_stat      = ( unsigned int* )( 0x01c40d3c );
    unsigned int* pll_div1      = ( unsigned int* )( 0x01c40d18 );
    unsigned int* pll_div2      = ( unsigned int* )( 0x01c40d1c );
    unsigned int* pll_bpdiv     = ( unsigned int* )( 0x01c40d2c );

    int pll2_freq = 27 * ( pll_mult + 1 );
    int DDR2_freq = pll2_freq / ( 2 * ( DDR2_div + 1 ) );
    int vpss_freq = pll2_freq / ( vpss_div + 1 );
    int bypass_div = 1;

    GEL_TextOut( "Setup PLL2 " );

    /*
     *  Step 0 - Ignore request if the PLL is already set as is
     */
    if ( ( ( *pll_ctl & 0x0100 ) >> 8 ) == clock_source )
    {
        if ( ( *pll_pllm & 0x3f ) == ( pll_mult & 0x3f ) )
        {
            if (   ( ( *pll_div1 & 0x1f ) == ( vpss_div & 0x1f ) )
                || ( ( *pll_div2 & 0x1f ) == ( DDR2_div & 0x1f ) ) )
            {
                GEL_TextOut( "(VPSS = %d MHz + ",,,,, vpss_freq );
                GEL_TextOut( "DDR2 Phy = %d MHz + ",,,,, DDR2_freq );
                if ( clock_source == 0 )
                    GEL_TextOut( "Onchip Oscillator)... " );
                else
                    GEL_TextOut( "External Clock)... " );

                GEL_TextOut( "[Already Set]\n" );
                return;
            }
        }
    }

    /*
     *  Step 0 - Stop all peripheral operations
     */

    /*
     *  Step 1 - Set clock mode
     */
    if ( clock_source == 0 )
        *pll_ctl &= ~0x0100;    // Onchip Oscillator
    else
        *pll_ctl |= 0x0100;     // External Clock

    /*
     *  Step 2 - Set PLL to bypass
     *         - Wait for PLL to stabilize
     */
    *pll_ctl &= ~0x0021;
    _wait( 150 );

    /*
     *  Step 3 - Reset PLL
     */
    *pll_ctl &= ~0x0008;

    /*
     *  Step 4 - Disable PLL
     *  Step 5 - Powerup PLL
     *  Step 6 - Enable PLL
     *  Step 7 - Wait for PLL to stabilize
     */
    *pll_ctl |= 0x0010;         // Disable PLL
    *pll_ctl &= ~0x0002;        // Power up PLL
    *pll_ctl &= ~0x0010;        // Enable PLL
    _wait( 150 );               // Wait for PLL to stabilize

    /*
     *  Step 8 - Load PLL multiplier
     */
    *pll_pllm = pll_mult & 0x3f;

    /*
     *  Step 9 - Load PLL dividers ( must be in a 1/3/6 ratio )
     *           1:DDR2, 2:VPSS-VPBE
     */
    *pll_bpdiv = 0x8000 | bypass_div;
    *pll_div1 = 0x8000 | ( vpss_div & 0x1f );
    *pll_div2 = 0x8000 | ( DDR2_div & 0x1f );
    *pll_cmd |= 0x0001;             // Set phase alignment
    while( ( *pll_stat & 1 ) != 0 );// Wait for phase alignment

    /*
     *  Step 10 - Wait for PLL to reset ( 2000 cycles )
     *  Step 11 - Release from reset
     */
    _wait( 2000 );
    *pll_ctl |= 0x0008;

    /*
     *  Step 12 - Wait for PLL to re-lock ( 2000 cycles )
     *  Step 13 - Switch out of BYPASS mode
     */
    _wait( 2000 );
    *pll_ctl |= 0x0001;