katmai.c

u-boot 源代码

		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
	unsigned long strap;

	/*-------------------------------------------------------------------+
	 *	The katmai board is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_sdstp1, strap);
	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
		return 0;
	}

	return 1;
}
#endif	/* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*-------------------------------------------------------------------+
	 * Disable everything
	 *-------------------------------------------------------------------*/
	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */

	/*-------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
	 * strapping options to not support sizes such as 128/256 MB.
	 *-------------------------------------------------------------------*/
	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
	out32r( PCIX0_PIM0LAH, 0 );
	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
	out32r( PCIX0_BAR0, 0 );

	/*-------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *-------------------------------------------------------------------*/
	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );

	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
}
#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

#if defined(CONFIG_PCI)
/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
int is_pci_host(struct pci_controller *hose)
{
	/* The katmai board is always configured as host. */
	return 1;
}

int katmai_pcie_card_present(int port)
{
	u32 val;

	val = in32(GPIO0_IR);
	switch (port) {
	case 0:
		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
	case 1:
		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
	case 2:
		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
	default:
		return 0;
	}
}

static struct pci_controller pcie_hose[3] = {{0},{0},{0}};

void pcie_setup_hoses(int busno)
{
	struct pci_controller *hose;
	int i, bus;
	char *env;
	unsigned int delay;

	/*
	 * assume we're called after the PCIX hose is initialized, which takes
	 * bus ID 0 and therefore start numbering PCIe's from 1.
	 */
	bus = busno;
	for (i = 0; i <= 2; i++) {
		/* Check for katmai card presence */
		if (!katmai_pcie_card_present(i))
			continue;

#ifdef PCIE_ENDPOINT
 		if (ppc440spe_init_pcie_endport(i)) {
#else
		if (ppc440spe_init_pcie_rootport(i)) {
#endif
			printf("PCIE%d: initialization failed\n", i);
			continue;
		}

		hose = &pcie_hose[i];
		hose->first_busno = bus;
		hose->last_busno = bus;
		hose->current_busno = bus;

		/* setup mem resource */
		pci_set_region(hose->regions + 0,
			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
			       CFG_PCIE_MEMSIZE,
			       PCI_REGION_MEM
			);
		hose->region_count = 1;
		pci_register_hose(hose);

#ifdef PCIE_ENDPOINT
		ppc440spe_setup_pcie_endpoint(hose, i);
		/*
		 * Reson for no scanning is endpoint can not generate
		 * upstream configuration accesses.
		 */
#else
		ppc440spe_setup_pcie_rootpoint(hose, i);

		env = getenv ("pciscandelay");
		if (env != NULL) {
			delay = simple_strtoul (env, NULL, 10);
			if (delay > 5)
				printf ("Warning, expect noticable delay before PCIe"
					"scan due to 'pciscandelay' value!\n");
			mdelay (delay * 1000);
		}

		/*
		 * Config access can only go down stream
		 */
		hose->last_busno = pci_hose_scan(hose);
		bus = hose->last_busno + 1;
#endif
	}
}
#endif	/* defined(CONFIG_PCI) */

int misc_init_f (void)
{
	uint reg;
#if defined(CONFIG_STRESS)
	uint i ;
	uint disp;
#endif

	/* minimal init for PCIe */
#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
	/* pci express 0 Endpoint Mode */
	mfsdr(SDR0_PE0DLPSET, reg);
	reg &= (~0x00400000);
	mtsdr(SDR0_PE0DLPSET, reg);
#else
	/* pci express 0 Rootpoint  Mode */
	mfsdr(SDR0_PE0DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE0DLPSET, reg);
#endif
	/* pci express 1 Rootpoint  Mode */
	mfsdr(SDR0_PE1DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE1DLPSET, reg);
	/* pci express 2 Rootpoint  Mode */
	mfsdr(SDR0_PE2DLPSET, reg);
	reg |= 0x00400000;
	mtsdr(SDR0_PE2DLPSET, reg);

#if defined(CONFIG_STRESS)
	/*
	 * All this setting done by linux only needed by stress an charac. test
	 * procedure
	 * PCIe 1 Rootpoint PCIe2 Endpoint
	 * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
	 */
	for (i=0,disp=0; i<8; i++,disp+=3) {
		mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
	}

	/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
	for (i=0,disp=0; i<4; i++,disp+=3) {
		mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
	}

	/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
	for (i=0,disp=0; i<4; i++,disp+=3) {
		mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
		reg |= 0x33000000;
		mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
	}

	reg = 0x21242222;
	mtsdr(SDR0_PE2UTLSET1, reg);
	reg = 0x11000000;
	mtsdr(SDR0_PE2UTLSET2, reg);
	/* pci express 1 Endpoint  Mode */
	reg = 0x00004000;
	mtsdr(SDR0_PE2DLPSET, reg);

	mtsdr(SDR0_UART1, 0x2080005a);	/* patch for TG */
#endif

	return 0;
}

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{
	return (ctrlc());
}
#endif