sdram.h

u-boot 源代码

/*
 * (C) Copyright 2006
 * Sylvie Gohl,             AMCC/IBM, [e-mail]
 * Jacqueline Pira-Ferriol, AMCC/IBM, [e-mail]
 * Thierry Roman,           AMCC/IBM, [e-mail]
 * Alain Saurel,            AMCC/IBM, [e-mail]
 * Robert Snyder,           AMCC/IBM, [e-mail]
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef _SPD_SDRAM_DENALI_H_
#define _SPD_SDRAM_DENALI_H_

#define ppcMsync	sync
#define ppcMbar		eieio

/* General definitions */
#define MAX_SPD_BYTE        128         /* highest SPD byte # to read */
#define DENALI_REG_NUMBER   45          /* 45 Regs in PPC440EPx Denali Core */
#define SUPPORTED_DIMMS_NB  7           /* Number of supported DIMM modules types */
#define SDRAM_NONE          0           /* No DIMM detected in Slot */
#define MAXRANKS            2           /* 2 ranks maximum */

/* Supported PLB Frequencies */
#define PLB_FREQ_133MHZ     133333333
#define PLB_FREQ_152MHZ     152000000
#define PLB_FREQ_160MHZ     160000000
#define PLB_FREQ_166MHZ     166666666

/* Denali Core Registers */
#define SDRAM_DCR_BASE 0x10

#define DDR_DCR_BASE 0x10
#define ddrcfga  (DDR_DCR_BASE+0x0)   /* DDR configuration address reg */
#define ddrcfgd  (DDR_DCR_BASE+0x1)   /* DDR configuration data reg    */

/*-----------------------------------------------------------------------------+
  | Values for ddrcfga register - indirect addressing of these regs
  +-----------------------------------------------------------------------------*/

#define DDR0_00                         0x00
#define DDR0_00_INT_ACK_MASK              0x7F000000 /* Write only */
#define DDR0_00_INT_ACK_ALL               0x7F000000
#define DDR0_00_INT_ACK_ENCODE(n)           ((((unsigned long)(n))&0x7F)<<24)
#define DDR0_00_INT_ACK_DECODE(n)           ((((unsigned long)(n))>>24)&0x7F)
/* Status */
#define DDR0_00_INT_STATUS_MASK           0x00FF0000 /* Read only */
/* Bit0. A single access outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT0           0x00010000
/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */
#define DDR0_00_INT_STATUS_BIT1           0x00020000
/* Bit2. Single correctable ECC event detected */
#define DDR0_00_INT_STATUS_BIT2           0x00040000
/* Bit3. Multiple correctable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT3           0x00080000
/* Bit4. Single uncorrectable ECC event detected. */
#define DDR0_00_INT_STATUS_BIT4           0x00100000
/* Bit5. Multiple uncorrectable ECC events detected. */
#define DDR0_00_INT_STATUS_BIT5           0x00200000
/* Bit6. DRAM initialization complete. */
#define DDR0_00_INT_STATUS_BIT6           0x00400000
/* Bit7. Logical OR of all lower bits. */
#define DDR0_00_INT_STATUS_BIT7           0x00800000

#define DDR0_00_INT_STATUS_ENCODE(n)        ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_00_INT_STATUS_DECODE(n)        ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_00_DLL_INCREMENT_MASK        0x00007F00
#define DDR0_00_DLL_INCREMENT_ENCODE(n)     ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_00_DLL_INCREMENT_DECODE(n)     ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_00_DLL_START_POINT_MASK      0x0000007F
#define DDR0_00_DLL_START_POINT_ENCODE(n)   ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_00_DLL_START_POINT_DECODE(n)   ((((unsigned long)(n))>>0)&0x7F)


#define DDR0_01                         0x01
#define DDR0_01_PLB0_DB_CS_LOWER_MASK     0x1F000000
#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n)  ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_01_PLB0_DB_CS_UPPER_MASK     0x001F0000
#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n)  ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n)  ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_01_OUT_OF_RANGE_TYPE_MASK    0x00000700 /* Read only */
#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n)               ((((unsigned long)(n))&0x7)<<8)
#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n)               ((((unsigned long)(n))>>8)&0x7)
#define DDR0_01_INT_MASK_MASK             0x000000FF
#define DDR0_01_INT_MASK_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_01_INT_MASK_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)
#define DDR0_01_INT_MASK_ALL_ON           0x000000FF
#define DDR0_01_INT_MASK_ALL_OFF          0x00000000

#define DDR0_02                         0x02
#define DDR0_02_MAX_CS_REG_MASK           0x02000000 /* Read only */
#define DDR0_02_MAX_CS_REG_ENCODE(n)        ((((unsigned long)(n))&0x2)<<24)
#define DDR0_02_MAX_CS_REG_DECODE(n)        ((((unsigned long)(n))>>24)&0x2)
#define DDR0_02_MAX_COL_REG_MASK          0x000F0000 /* Read only */
#define DDR0_02_MAX_COL_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<16)
#define DDR0_02_MAX_COL_REG_DECODE(n)       ((((unsigned long)(n))>>16)&0xF)
#define DDR0_02_MAX_ROW_REG_MASK          0x00000F00 /* Read only */
#define DDR0_02_MAX_ROW_REG_ENCODE(n)       ((((unsigned long)(n))&0xF)<<8)
#define DDR0_02_MAX_ROW_REG_DECODE(n)       ((((unsigned long)(n))>>8)&0xF)
#define DDR0_02_START_MASK                0x00000001
#define DDR0_02_START_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
#define DDR0_02_START_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)
#define DDR0_02_START_OFF                 0x00000000
#define DDR0_02_START_ON                  0x00000001

#define DDR0_03                         0x03
#define DDR0_03_BSTLEN_MASK               0x07000000
#define DDR0_03_BSTLEN_ENCODE(n)            ((((unsigned long)(n))&0x7)<<24)
#define DDR0_03_BSTLEN_DECODE(n)            ((((unsigned long)(n))>>24)&0x7)
#define DDR0_03_CASLAT_MASK               0x00070000
#define DDR0_03_CASLAT_ENCODE(n)            ((((unsigned long)(n))&0x7)<<16)
#define DDR0_03_CASLAT_DECODE(n)            ((((unsigned long)(n))>>16)&0x7)
#define DDR0_03_CASLAT_LIN_MASK           0x00000F00
#define DDR0_03_CASLAT_LIN_ENCODE(n)        ((((unsigned long)(n))&0xF)<<8)
#define DDR0_03_CASLAT_LIN_DECODE(n)        ((((unsigned long)(n))>>8)&0xF)
#define DDR0_03_INITAREF_MASK             0x0000000F
#define DDR0_03_INITAREF_ENCODE(n)          ((((unsigned long)(n))&0xF)<<0)
#define DDR0_03_INITAREF_DECODE(n)          ((((unsigned long)(n))>>0)&0xF)

#define DDR0_04                         0x04
#define DDR0_04_TRC_MASK                  0x1F000000
#define DDR0_04_TRC_ENCODE(n)               ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_04_TRC_DECODE(n)               ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_04_TRRD_MASK                 0x00070000
#define DDR0_04_TRRD_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
#define DDR0_04_TRRD_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
#define DDR0_04_TRTP_MASK                 0x00000700
#define DDR0_04_TRTP_ENCODE(n)              ((((unsigned long)(n))&0x7)<<8)
#define DDR0_04_TRTP_DECODE(n)              ((((unsigned long)(n))>>8)&0x7)

#define DDR0_05                         0x05
#define DDR0_05_TMRD_MASK                 0x1F000000
#define DDR0_05_TMRD_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_05_TMRD_DECODE(n)              ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_05_TEMRS_MASK                0x00070000
#define DDR0_05_TEMRS_ENCODE(n)             ((((unsigned long)(n))&0x7)<<16)
#define DDR0_05_TEMRS_DECODE(n)             ((((unsigned long)(n))>>16)&0x7)
#define DDR0_05_TRP_MASK                  0x00000F00
#define DDR0_05_TRP_ENCODE(n)               ((((unsigned long)(n))&0xF)<<8)
#define DDR0_05_TRP_DECODE(n)               ((((unsigned long)(n))>>8)&0xF)
#define DDR0_05_TRAS_MIN_MASK             0x000000FF
#define DDR0_05_TRAS_MIN_ENCODE(n)          ((((unsigned long)(n))&0xFF)<<0)
#define DDR0_05_TRAS_MIN_DECODE(n)          ((((unsigned long)(n))>>0)&0xFF)

#define DDR0_06                         0x06
#define DDR0_06_WRITEINTERP_MASK          0x01000000
#define DDR0_06_WRITEINTERP_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
#define DDR0_06_WRITEINTERP_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
#define DDR0_06_TWTR_MASK                 0x00070000
#define DDR0_06_TWTR_ENCODE(n)              ((((unsigned long)(n))&0x7)<<16)
#define DDR0_06_TWTR_DECODE(n)              ((((unsigned long)(n))>>16)&0x7)
#define DDR0_06_TDLL_MASK                 0x0000FF00
#define DDR0_06_TDLL_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_06_TDLL_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)
#define DDR0_06_TRFC_MASK                 0x0000007F
#define DDR0_06_TRFC_ENCODE(n)              ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_06_TRFC_DECODE(n)              ((((unsigned long)(n))>>0)&0x7F)

#define DDR0_07                         0x07
#define DDR0_07_NO_CMD_INIT_MASK          0x01000000
#define DDR0_07_NO_CMD_INIT_ENCODE(n)       ((((unsigned long)(n))&0x1)<<24)
#define DDR0_07_NO_CMD_INIT_DECODE(n)       ((((unsigned long)(n))>>24)&0x1)
#define DDR0_07_TFAW_MASK                 0x001F0000
#define DDR0_07_TFAW_ENCODE(n)              ((((unsigned long)(n))&0x1F)<<16)
#define DDR0_07_TFAW_DECODE(n)              ((((unsigned long)(n))>>16)&0x1F)
#define DDR0_07_AUTO_REFRESH_MODE_MASK    0x00000100
#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8)
#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1)
#define DDR0_07_AREFRESH_MASK             0x00000001
#define DDR0_07_AREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<0)
#define DDR0_07_AREFRESH_DECODE(n)          ((((unsigned long)(n))>>0)&0x1)

#define DDR0_08                         0x08
#define DDR0_08_WRLAT_MASK                0x07000000
#define DDR0_08_WRLAT_ENCODE(n)             ((((unsigned long)(n))&0x7)<<24)
#define DDR0_08_WRLAT_DECODE(n)             ((((unsigned long)(n))>>24)&0x7)
#define DDR0_08_TCPD_MASK                 0x00FF0000
#define DDR0_08_TCPD_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_08_TCPD_DECODE(n)              ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_08_DQS_N_EN_MASK             0x00000100
#define DDR0_08_DQS_N_EN_ENCODE(n)          ((((unsigned long)(n))&0x1)<<8)
#define DDR0_08_DQS_N_EN_DECODE(n)          ((((unsigned long)(n))>>8)&0x1)
#define DDR0_08_DDRII_SDRAM_MODE_MASK     0x00000001
#define DDR0_08_DDRII_ENCODE(n)             ((((unsigned long)(n))&0x1)<<0)
#define DDR0_08_DDRII_DECODE(n)             ((((unsigned long)(n))>>0)&0x1)

#define DDR0_09                         0x09
#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK  0x1F000000
#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_09_RTT_0_MASK                0x00030000
#define DDR0_09_RTT_0_ENCODE(n)             ((((unsigned long)(n))&0x3)<<16)
#define DDR0_09_RTT_0_DECODE(n)             ((((unsigned long)(n))>>16)&0x3)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK  0x00007F00
#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8)
#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F)
#define DDR0_09_WR_DQS_SHIFT_MASK         0x0000007F
#define DDR0_09_WR_DQS_SHIFT_ENCODE(n)      ((((unsigned long)(n))&0x7F)<<0)
#define DDR0_09_WR_DQS_SHIFT_DECODE(n)      ((((unsigned long)(n))>>0)&0x7F)

#define DDR0_10                         0x0A
#define DDR0_10_WRITE_MODEREG_MASK        0x00010000 /* Write only */
#define DDR0_10_WRITE_MODEREG_ENCODE(n)     ((((unsigned long)(n))&0x1)<<16)
#define DDR0_10_WRITE_MODEREG_DECODE(n)     ((((unsigned long)(n))>>16)&0x1)
#define DDR0_10_CS_MAP_MASK               0x00000300
#define DDR0_10_CS_MAP_NO_MEM             0x00000000
#define DDR0_10_CS_MAP_RANK0_INSTALLED    0x00000100
#define DDR0_10_CS_MAP_RANK1_INSTALLED    0x00000200
#define DDR0_10_CS_MAP_ENCODE(n)            ((((unsigned long)(n))&0x3)<<8)
#define DDR0_10_CS_MAP_DECODE(n)            ((((unsigned long)(n))>>8)&0x3)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK  0x0000001F
#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0)
#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F)

#define DDR0_11                         0x0B
#define DDR0_11_SREFRESH_MASK             0x01000000
#define DDR0_11_SREFRESH_ENCODE(n)          ((((unsigned long)(n))&0x1)<<24)
#define DDR0_11_SREFRESH_DECODE(n)          ((((unsigned long)(n))>>24)&0x1F)
#define DDR0_11_TXSNR_MASK                0x00FF0000
#define DDR0_11_TXSNR_ENCODE(n)             ((((unsigned long)(n))&0xFF)<<16)
#define DDR0_11_TXSNR_DECODE(n)             ((((unsigned long)(n))>>16)&0xFF)
#define DDR0_11_TXSR_MASK                 0x0000FF00
#define DDR0_11_TXSR_ENCODE(n)              ((((unsigned long)(n))&0xFF)<<8)
#define DDR0_11_TXSR_DECODE(n)              ((((unsigned long)(n))>>8)&0xFF)

#define DDR0_12                         0x0C
#define DDR0_12_TCKE_MASK                 0x0000007
#define DDR0_12_TCKE_ENCODE(n)              ((((unsigned long)(n))&0x7)<<0)
#define DDR0_12_TCKE_DECODE(n)              ((((unsigned long)(n))>>0)&0x7)

#define DDR0_13                         0x0D

#define DDR0_14                         0x0E
#define DDR0_14_DLL_BYPASS_MODE_MASK      0x01000000
#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n)   ((((unsigned long)(n))&0x1)<<24)
#define DDR0_14_DLL_BYPASS_MODE_DECODE(n)   ((((unsigned long)(n))>>24)&0x1)
#define DDR0_14_REDUC_MASK                0x00010000
#define DDR0_14_REDUC_64BITS              0x00000000