p3mx.c

u-boot 源代码

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, [e-mail].
 *
 * Based on original work by
 *	Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
 *	Josh Huber, (C) Copyright 2001 Mission Critical Linux, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * modifications for the DB64360 eval board based by [e-mail]
 * modifications for the cpci750 by [e-mail]
 * modifications for the P3M750 by [e-mail]
 */

/*
 * p3m750.c - main board support/init for the Prodrive p3m750/p3m7448.
 */

#include <common.h>
#include <74xx_7xx.h>
#include "../../Marvell/include/memory.h"
#include "../../Marvell/include/pci.h"
#include "../../Marvell/include/mv_gen_reg.h"
#include <net.h>
#include <i2c.h>

#include "eth.h"
#include "mpsc.h"
#include "64460.h"
#include "mv_regs.h"
#include "p3mx.h"

DECLARE_GLOBAL_DATA_PTR;

#undef	DEBUG
/*#define	DEBUG */

#ifdef CONFIG_PCI
#define	MAP_PCI
#endif /* of CONFIG_PCI */

#ifdef DEBUG
#define DP(x) x
#else
#define DP(x)
#endif

extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern flash_info_t flash_info[];

/* ------------------------------------------------------------------------- */

/* this is the current GT register space location */
/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */

/* Unfortunately, we cant change it while we are in flash, so we initialize it
 * to the "final" value. This means that any debug_led calls before
 * board_early_init_f wont work right (like in cpu_init_f).
 * See also my_remap_gt_regs below. (NTL)
 */

void board_prebootm_init (void);
unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
int display_mem_map (void);
void set_led(int);

/* ------------------------------------------------------------------------- */

/*
 * This is a version of the GT register space remapping function that
 * doesn't touch globals (meaning, it's ok to run from flash.)
 *
 * Unfortunately, this has the side effect that a writable
 * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
 */

void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
{
	u32 temp;

	/* check and see if it's already moved */
	temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
	if ((temp & 0xffff) == new_loc >> 16)
		return;

	temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
		0xffff0000) | (new_loc >> 16);

	out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);

	while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
}

#ifdef CONFIG_PCI

static void gt_pci_config (void)
{
	unsigned int stat;
	unsigned int val = 0x00fff864;	/* DINK32: BusNum 23:16,  DevNum 15:11, */
					/* FuncNum 10:8, RegNum 7:2 */

	/*
	 * In PCIX mode devices provide their own bus and device numbers.
	 * We query the Discovery II's
	 * config registers by writing ones to the bus and device.
	 * We then update the Virtual register with the correct value for the
	 * bus and device.
	 */
	if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);

		GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);

		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
			      (stat & 0xffff0000) | CFG_PCI_IDSEL);

	}
	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
		GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);

		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
	}

	/* Enable master */
	PCI_MASTER_ENABLE (0, SELF);
	PCI_MASTER_ENABLE (1, SELF);

	/* Enable PCI0/1 Mem0 and IO 0 disable all others */
	GT_REG_READ (BASE_ADDR_ENABLE, &stat);
	stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) |
		(1 << 18);
	stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
	GT_REG_WRITE (BASE_ADDR_ENABLE, stat);

	/* ronen:
	 * add write to pci remap registers for 64460.
	 * in 64360 when writing to pci base go and overide remap automaticaly,
	 * in 64460 it doesn't
	 */
	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);

	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);

	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);

	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);

	/* PCI interface settings */
	/* Timeout set to retry forever */
	GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
	GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);

	/* ronen - enable only CS0 and Internal reg!! */
	GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
	GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);

	/* ronen:
	 * update the pci internal registers base address.
	 */
#ifdef MAP_PCI
	for (stat = 0; stat <= PCI_HOST1; stat++)
		pciWriteConfigReg (stat,
				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
				   SELF, CFG_GT_REGS);
#endif

}
#endif

/* Setup CPU interface paramaters */
static void gt_cpu_config (void)
{
	cpu_t cpu = get_cpu_type ();
	ulong tmp;

	/* cpu configuration register */
	tmp = GTREGREAD (CPU_CONFIGURATION);
	/* set the SINGLE_CPU bit  see MV64460 */
#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
	tmp |= CPU_CONF_SINGLE_CPU;
#endif
	tmp &= ~CPU_CONF_AACK_DELAY_2;
	tmp |= CPU_CONF_DP_VALID;
	tmp |= CPU_CONF_AP_VALID;
	tmp |= CPU_CONF_PIPELINE;
	GT_REG_WRITE (CPU_CONFIGURATION, tmp);	/* Marvell (VXWorks) writes 0x20220FF */

	/* CPU master control register */
	tmp = GTREGREAD (CPU_MASTER_CONTROL);
	tmp |= CPU_MAST_CTL_ARB_EN;

	if ((cpu == CPU_7400) ||
	    (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {

		tmp |= CPU_MAST_CTL_CLEAN_BLK;
		tmp |= CPU_MAST_CTL_FLUSH_BLK;

	} else {
		/* cleanblock must be cleared for CPUs
		 * that do not support this command (603e, 750)
		 * see Res#1 */
		tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
		tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
	}
	GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
}

/*
 * board_early_init_f.
 *
 * set up gal. device mappings, etc.
 */
int board_early_init_f (void)
{
	/* set up the GT the way the kernel wants it
	 * the call to move the GT register space will obviously
	 * fail if it has already been done, but we're going to assume
	 * that if it's not at the power-on location, it's where we put
	 * it last time. (huber)
	 */
	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);

#ifdef CONFIG_PCI
	gt_pci_config ();
#endif
	/* mask all external interrupt sources */
	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
	/* new in >MV6436x */
	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
	/* --------------------- */
	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
	GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);

	/* Device and Boot bus settings
	 */
	memoryMapDeviceSpace(DEVICE0, 0, 0);
	GT_REG_WRITE(DEVICE_BANK0PARAMETERS, 0);
	memoryMapDeviceSpace(DEVICE1, 0, 0);
	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, 0);
	memoryMapDeviceSpace(DEVICE2, 0, 0);
	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, 0);
	memoryMapDeviceSpace(DEVICE3, 0, 0);
	GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);

	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);

	gt_cpu_config();

	/* MPP setup */
	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);

	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);

	set_led(LED_RED);

	return 0;
}

/* various things to do after relocation */

int misc_init_r ()
{
	u8 val;

	icache_enable ();
#ifdef CFG_L2
	l2cache_enable ();
#endif
#ifdef CONFIG_MPSC
	mpsc_sdma_init ();
	mpsc_init2 ();
#endif

	/*
	 * Enable trickle changing in RTC upon powerup
	 * No diode, 250 ohm series resistor
	 */
	val = 0xa5;
	i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);

	return 0;
}

int board_early_init_r(void)
{
	/* now relocate the debug serial driver */
	mpsc_putchar += gd->reloc_off;
	mpsc_getchar += gd->reloc_off;
	mpsc_test_char += gd->reloc_off;

	return 0;
}

void after_reloc (ulong dest_addr, gd_t * gd)
{
	memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);

/*	display_mem_map(); */

	/* now, jump to the main U-Boot board init code */
	set_led(LED_GREEN);
	board_init_r (gd, dest_addr);
	/* NOTREACHED */
}

/*
 * Check Board Identity:
 * right now, assume borad type. (there is just one...after all)
 */

int checkboard (void)
{
	char *s = getenv("serial#");

	printf("Board: %s", CFG_BOARD_NAME);

	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

void set_led(int col)
{
	int tmp;
	int on_pin;
	int off_pin;

	/* Program Mpp[22] as Gpp[22]
	 * Program Mpp[23] as Gpp[23]
	 */
	tmp = GTREGREAD(MPP_CONTROL2);
	tmp &= 0x00ffffff;
	GT_REG_WRITE(MPP_CONTROL2,tmp);

	/* Program Gpp[22] and Gpp[23] as output
	 */
	tmp = GTREGREAD(GPP_IO_CONTROL);
	tmp |= 0x00C00000;
	GT_REG_WRITE(GPP_IO_CONTROL, tmp);

	/* Program Gpp[22] and Gpp[23] as active high
	 */
	tmp = GTREGREAD(GPP_LEVEL_CONTROL);
	tmp &= 0xff3fffff;
	GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp);

	switch(col) {
	default:
	case LED_OFF :
		on_pin  = 0;
		off_pin = ((1 << 23) | (1 << 22));
		break;
	case LED_RED :
		on_pin  = (1 << 23);
		off_pin = (1 << 22);
		break;
	case LED_GREEN :
		on_pin  = (1 << 22);
		off_pin = (1 << 23);
		break;
	case LED_ORANGE :
		on_pin  = ((1 << 23) | (1 << 22));
		off_pin = 0;
		break;
	}

	/* Set output Gpp[22] and Gpp[23]
	 */
	tmp = GTREGREAD(GPP_VALUE);
	tmp |= on_pin;
	tmp &= ~off_pin;
	GT_REG_WRITE(GPP_VALUE, tmp);
}

int display_mem_map (void)
{
	int i;
	unsigned int base, size, width;
#ifdef CONFIG_PCI
	int j;
#endif

	/* SDRAM */
	printf ("SD (DDR) RAM\n");
	for (i = 0; i <= BANK3; i++) {
		base = memoryGetBankBaseAddress (i);
		size = memoryGetBankSize (i);
		if (size != 0)
			printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
				i, base, size >> 20);
	}
#ifdef CONFIG_PCI