📄 ixparityenacc.h
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IX_PARITYENACC_SWCP, /**< SWCP */ IX_PARITYENACC_AQM, /**< AQM */ IX_PARITYENACC_MCU_SBIT, /**< DDR Memory Controller Unit - Single bit parity */ IX_PARITYENACC_MCU_MBIT, /**< DDR Memory Controller Unit - Multi bit parity */ IX_PARITYENACC_MCU_OVERFLOW, /**< DDR Memory Controller Unit - Parity errors in excess of two */ IX_PARITYENACC_EBC_CS, /**< Expansion Bus Controller - Chip Select */ IX_PARITYENACC_EBC_EXTMST /**< Expansion Bus Controller - External Master */} IxParityENAccParityErrorSource;/** * @ingroup IxParityENAcc * * @enum IxParityENAccParityErrorAccess * * @brief The type of access resulting in parity error */typedef enum /**< IxParityENAccParityErrorAccess */{ IX_PARITYENACC_READ, /**< Read Access */ IX_PARITYENACC_WRITE /**< Write Access */} IxParityENAccParityErrorAccess;/** * @ingroup IxParityENAcc * * @typedef IxParityENAccParityErrorAddress * * @brief The memory location which has parity error */typedef UINT32 IxParityENAccParityErrorAddress;/** * @ingroup IxParityENAcc * * @typedef IxParityENAccParityErrorData * * @brief The data read from the memory location which has parity error */typedef UINT32 IxParityENAccParityErrorData;/** * @ingroup IxParityENAcc * * @enum IxParityENAccParityErrorRequester * * @brief The requester interface through which the SDRAM memory access * resulted in the parity error. */typedef enum /**< IxParityENAccParityErrorRequester */{ IX_PARITYENACC_MPI, /**< Direct Memory Port Interface */ IX_PARITYENACC_AHB_BUS /**< South or North AHB Bus */} IxParityENAccParityErrorRequester;/** * @ingroup IxParityENAcc * * @enum IxParityENAccAHBErrorMaster * * @brief The Master on the AHB bus interface whose transaction might have * resulted in the parity error notification to XScale. */typedef enum /**< IxParityENAccAHBErrorMaster */{ IX_PARITYENACC_AHBN_MST_NPE_A, /**< NPE - A */ IX_PARITYENACC_AHBN_MST_NPE_B, /**< NPE - B */ IX_PARITYENACC_AHBN_MST_NPE_C, /**< NPE - C */ IX_PARITYENACC_AHBS_MST_XSCALE, /**< XScale Bus Interface Unit */ IX_PARITYENACC_AHBS_MST_PBC, /**< PCI Bus Controller */ IX_PARITYENACC_AHBS_MST_EBC, /**< Expansion Bus Controller */ IX_PARITYENACC_AHBS_MST_AHB_BRIDGE, /**< AHB Bridge */ IX_PARITYENACC_AHBS_MST_USBH /**< USB Host Controller */} IxParityENAccAHBErrorMaster;/** * @ingroup IxParityENAcc * * @enum IxParityENAccAHBErrorSlave * * @brief The Slave on the AHB bus interface whose transaction might have * resulted in the parity error notification to XScale. */typedef enum /**< IxParityENAccAHBErrorSlave */{ IX_PARITYENACC_AHBN_SLV_MCU, /**< Memory Control Unit */ IX_PARITYENACC_AHBN_SLV_AHB_BRIDGE, /**< AHB Bridge */ IX_PARITYENACC_AHBS_SLV_MCU, /**< XScale Bus Interface Unit */ IX_PARITYENACC_AHBS_SLV_APB_BRIDGE, /**< APB Bridge */ IX_PARITYENACC_AHBS_SLV_AQM, /**< AQM */ IX_PARITYENACC_AHBS_SLV_RSA, /**< RSA (Crypto Bus) */ IX_PARITYENACC_AHBS_SLV_PBC, /**< PCI Bus Controller */ IX_PARITYENACC_AHBS_SLV_EBC, /**< Expansion Bus Controller */ IX_PARITYENACC_AHBS_SLV_USBH /**< USB Host Controller */} IxParityENAccAHBErrorSlave;/** * @ingroup IxParityENAcc * * @struct IxParityENAccAHBErrorTransaction * * @brief The Master and Slave on the AHB bus interface whose transaction might * have resulted in the parity error notification to XScale. * * NOTE: This information may be used in the data abort exception handler * to differentiate between the XScale and non-XScale access to the SDRAM * memory. */typedef struct /**< IxParityENAccAHBErrorTransaction */{ IxParityENAccAHBErrorMaster ahbErrorMaster; /**< Master on AHB bus */ IxParityENAccAHBErrorSlave ahbErrorSlave; /**< Slave on AHB bus */} IxParityENAccAHBErrorTransaction;/** * @ingroup IxParityENAcc * * @struct IxParityENAccParityErrorContextMessage * * @brief Parity Error Context Message */typedef struct /**< IxParityENAccParityErrorContextMessage */{ IxParityENAccParityErrorSource pecParitySource; /**< Source info of parity error */ IxParityENAccParityErrorAccess pecAccessType; /**< Read or Write Access Read - NPE, SWCP, AQM, DDR MCU, Exp Bus Ctrlr (Outbound) Write - DDR MCU, Exp Bus Ctrlr (Inbound i.e., External Master) */ IxParityENAccParityErrorAddress pecAddress; /**< Address faulty location Valid only for AQM, DDR MCU, Exp Bus Ctrlr */ IxParityENAccParityErrorData pecData; /**< Data read from the faulty location Valid only for AQM and DDR MCU For DDR MCU it is the bit location of the Single-bit parity */ IxParityENAccParityErrorRequester pecRequester; /**< Requester of SDRAM memory access Valid only for the DDR MCU */ IxParityENAccAHBErrorTransaction ahbErrorTran; /**< Master and Slave information on the last AHB Error Transaction */} IxParityENAccParityErrorContextMessage;/** * @ingroup IxParityENAcc * * @typedef IxParityENAccCallback * * @brief This prototype shows the format of a callback function. * * The callback will be used to notify the parity error to the client application. * The callback will be registered by @ref ixParityENAccCallbackRegister. * * It will be called from an ISR when a parity error is detected and thus * needs to follow the interrupt callable function conventions. * */typedef void (*IxParityENAccCallback) (void);/* * Prototypes for interface functions. *//** * @ingroup IxParityENAcc * * @fn IxParityENAccStatus ixParityENAccInit(void) * * @brief This function will initialise the IxParityENAcc component. * * This function will initialise the IxParityENAcc component. It should only be * called once, prior to using the IxParityENAcc component. * * <OL><LI>It initialises the internal data structures, registers the ISR that * will be triggered when a parity error occurs in IXP4xx silicon.</LI></OL> * * @li Re-entrant : No * @li ISR Callable : No * * @return @li IX_PARITYENACC_SUCCESS - Initialization is successful * @li IX_PARITYENACC_ALREADY_INITIALISED - The access layer has already * been initialized * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the * operation didn't succeed on the hardware. Refer to error trace/log * for details. */PUBLIC IxParityENAccStatus ixParityENAccInit(void);/** * @ingroup IxParityENAcc * * @fn IxParityENAccStatus ixParityENAccCallbackRegister ( IxParityENAccCallback parityErrNfyCallBack) * * @brief This function will register a new callback with IxParityENAcc component. * It can also reregister a new callback replacing the old callback. * * @param parityErrNfyCallBack [in] - This parameter will specify the call-back * function supplied by the client application. * * This interface registers the user application supplied call-back handler with * the parity error handling access component after the init. * * The callback function will be called from an ISR that will be triggered by the * parity error in the IXP400 silicon. * * The following actions will be performed by this function: * <OL><LI>Check for the prior initialisation of the module before registering or * re-registering of the callback. * Check for parity error detection disabled before re-registration of the callback. * </LI></OL> * * @li Re-entrant : No * @li ISR Callable : No * * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the * registration is successful. * @li IX_PARITYENACC_INVALID_PARAMETERS - Request failed due to NULL * parameter passed. * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the * parity error detection not yet disabled. * @li IX_PARITYENACC_NOT_INITIALISED - The operation requested prior to * the initialisation of the access layer. */PUBLIC IxParityENAccStatus ixParityENAccCallbackRegister ( IxParityENAccCallback parityErrNfyCallBack);/** * @ingroup IxParityENAcc * * @fn IxParityENAccStatus ixParityENAccParityDetectionConfigure ( const IxParityENAccHWParityConfig *hwParityConfig) * * @brief This interface allows the client application to enable the parity * error detection on the underlying hardware block. * * @param hwParityConfig [in] - Hardware blocks for which the parity error * detection is to be enabled or disabled. * * The client application allocates and provides the reference to the buffer. * * It will also verify whether the specific hardware block is functional or not. * * NOTE: Failure in enabling or disabling of one or more components result in * trace message but still returns IX_PARITYENACC_SUCCESS. Refer to the function * @ref ixParityENAccParityDetectionQuery on how to verify the failures while * enabling/disabling paritys error detection. * * It shall be invoked after the Init and CallbackRegister functions but before * any other function of the IxParityENAcc layer. * * @li Re-entrant : No * @li ISR Callable : No * * @return @li IX_PARITYENACC_SUCCESS - The parameters check passed and the * request to enable/disable is successful. * @li IX_PARITYENACC_INVALID_PARAMETERS-The request failed due to * NULL parameter supplied. * @li IX_PARITYENACC_OPERATION_FAILED - The request failed because the * operation didn't succeed on the hardware.
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