ixhssacc.h

u-boot 源代码

/**
 * @file IxHssAcc.h
 * 
 * @date 07-DEC-2001
 *
 * @brief This file contains the public API of the IXP400 HSS Access
 * component
 *
 * 
 * @par
 * IXP400 SW Release version 2.0
 * 
 * -- Copyright Notice --
 * 
 * @par
 * Copyright 2001-2005, Intel Corporation.
 * All rights reserved.
 * 
 * @par
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the Intel Corporation nor the names of its contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 * 
 * @par
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 * 
 * @par
 * -- End of Copyright Notice --
*/
 
/* ------------------------------------------------------
   Doxygen group definitions
   ------------------------------------------------------ */
/**
 * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API
 *
 * @brief The public API for the IXP400 HssAccess component
 *
 * IxHssAcc is the access layer to the HSS packetised and channelised
 * services
 * 
 * <b> Design Notes </b><br>
 * <UL>
 * <LI>When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of 
 *     the transmitted data is not preserved. All raw data that is transmitted 
 *     will be received in proper order by the receiver, but the first bit of 
 *     the packet may be seen at any offset within a byte; all subsequent bytes 
 *     will have the same offset for the duration of the packet. The same offset 
 *     also applies to all subsequent packets received on the packet-pipe too. 
 *     (Similar results will occur for data received from remote end.) While 
 *     this behavior will also occur for 56Kbps HDLC mode, the HDLC 
 *     encoding/decoding will preserve the original byte alignment at the 
 *     receiver end.
 * </UL>
 *
 * <b> 56Kbps Packetised Service Bandwidth Limitation </b><br>
 * <UL>
 * <LI>IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate
 *     for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e.
 *     it supports 56Kbps packetised service on up to 8 T1 trunks. It does
 *     not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per 
 *     HSS port) unless those trunks are running 'fractional E1' with maximum 
 *     aggregate rate of 12.288 Mbps in each direction.<br>
 *     [1] 12.288Mbps = 1.536Mbp * 8 T1
 * </UL>
 * @{ */

#ifndef IXHSSACC_H
#define IXHSSACC_H

#include "IxOsal.h"

/*
 * #defines for function return types, etc.
 */

/**
 * @def IX_HSSACC_TSLOTS_PER_HSS_PORT
 *
 * @brief The max number of TDM timeslots supported per HSS port - 4E1's =
 *  32x4 = 128 
 */
#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128

/* -----------------------------------------------------------
   The following are HssAccess return values returned through 
   service interfaces. The globally defined IX_SUCCESS (0) and
   IX_FAIL (1) in IxOsalTypes.h are also used.
   ----------------------------------------------------------- */
/**
 * @def IX_HSSACC_PARAM_ERR
 *
 * @brief HssAccess function return value for a parameter error
 */
#define IX_HSSACC_PARAM_ERR 2

/**
 * @def IX_HSSACC_RESOURCE_ERR
 *
 * @brief HssAccess function return value for a resource error
 */
#define IX_HSSACC_RESOURCE_ERR 3

/**
 * @def IX_HSSACC_PKT_DISCONNECTING
 *
 * @brief Indicates that a disconnect call is progressing and will 
 * disconnect soon
 */
#define IX_HSSACC_PKT_DISCONNECTING 4

/**
 * @def IX_HSSACC_Q_WRITE_OVERFLOW
 *
 * @brief Indicates that an attempt to Tx or to replenish an 
 * RxFree Q failed due to Q overflow.  
 */
#define IX_HSSACC_Q_WRITE_OVERFLOW 5

/* -------------------------------------------------------------------
   The following errors are HSS/NPE errors returned on error retrieval
   ------------------------------------------------------------------- */
/**
 * @def IX_HSSACC_NO_ERROR
 *
 * @brief HSS port no error present
 */
#define IX_HSSACC_NO_ERROR 0

/**
 * @def IX_HSSACC_TX_FRM_SYNC_ERR
 *
 * @brief HSS port TX Frame Sync error
 */
#define IX_HSSACC_TX_FRM_SYNC_ERR 1

/**
 * @def IX_HSSACC_TX_OVER_RUN_ERR
 *
 * @brief HSS port TX over-run error
 */
#define IX_HSSACC_TX_OVER_RUN_ERR 2

/**
 * @def IX_HSSACC_CHANNELISED_SW_TX_ERR
 *
 * @brief NPE software error in channelised TX
 */
#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3

/**
 * @def IX_HSSACC_PACKETISED_SW_TX_ERR
 *
 * @brief NPE software error in packetised TX
 */
#define IX_HSSACC_PACKETISED_SW_TX_ERR 4

/**
 * @def IX_HSSACC_RX_FRM_SYNC_ERR
 *
 * @brief HSS port RX Frame Sync error
 */
#define IX_HSSACC_RX_FRM_SYNC_ERR 5

/**
 * @def IX_HSSACC_RX_OVER_RUN_ERR
 *
 * @brief HSS port RX over-run error
 */
#define IX_HSSACC_RX_OVER_RUN_ERR 6

/**
 * @def IX_HSSACC_CHANNELISED_SW_RX_ERR
 *
 * @brief NPE software error in channelised RX
 */
#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7

/**
 * @def IX_HSSACC_PACKETISED_SW_RX_ERR
 *
 * @brief NPE software error in packetised TX
 */
#define IX_HSSACC_PACKETISED_SW_RX_ERR 8

/* -----------------------------------
   Packetised service specific defines
   ----------------------------------- */

/**
 * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE
 *
 * @brief Minimum size of the Rx mbuf in bytes which the client must supply 
 * to the component. 
 */
#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64

/* --------------------------------------------------------------------
   Enumerated Types - these enumerated values may be used in setting up
   the contents of hardware registers
   -------------------------------------------------------------------- */
/**
 * @enum IxHssAccHssPort
 * @brief The HSS port ID - There are two identical ports (0-1). 
 * 
 */
typedef enum
{
    IX_HSSACC_HSS_PORT_0,   /**< HSS Port 0 */
    IX_HSSACC_HSS_PORT_1,   /**< HSS Port 1 */
    IX_HSSACC_HSS_PORT_MAX  /**< Delimiter for error checks */
} IxHssAccHssPort;

/**
 * @enum IxHssAccHdlcPort
 * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per 
 * HSS port and they correspond to the 4 E1/T1 trunks.
 * 
 */
typedef enum
{
   IX_HSSACC_HDLC_PORT_0,   /**< HDLC Port 0 */
   IX_HSSACC_HDLC_PORT_1,   /**< HDLC Port 1 */
   IX_HSSACC_HDLC_PORT_2,   /**< HDLC Port 2 */
   IX_HSSACC_HDLC_PORT_3,   /**< HDLC Port 3 */
   IX_HSSACC_HDLC_PORT_MAX  /**< Delimiter for error checks */
} IxHssAccHdlcPort;

/**
 * @enum IxHssAccTdmSlotUsage
 * @brief The HSS TDM stream timeslot assignment types
 *
 */
typedef enum
{
    IX_HSSACC_TDMMAP_UNASSIGNED,    /**< Unassigned */
    IX_HSSACC_TDMMAP_HDLC,          /**< HDLC - packetised */
    IX_HSSACC_TDMMAP_VOICE56K,      /**< Voice56K - channelised */
    IX_HSSACC_TDMMAP_VOICE64K,      /**< Voice64K - channelised */
    IX_HSSACC_TDMMAP_MAX            /**< Delimiter for error checks */
} IxHssAccTdmSlotUsage;

/**
 * @enum IxHssAccFrmSyncType
 * @brief The HSS frame sync pulse type
 *
 */
typedef enum
{
    IX_HSSACC_FRM_SYNC_ACTIVE_LOW,   /**< Frame sync is sampled low */
    IX_HSSACC_FRM_SYNC_ACTIVE_HIGH,  /**< sampled high */
    IX_HSSACC_FRM_SYNC_FALLINGEDGE,  /**< sampled on a falling edge */
    IX_HSSACC_FRM_SYNC_RISINGEDGE,   /**< sampled on a rising edge */
    IX_HSSACC_FRM_SYNC_TYPE_MAX      /**< Delimiter for error checks */
} IxHssAccFrmSyncType;

/**
 * @enum IxHssAccFrmSyncEnable
 * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is
 * used
 * */
typedef enum
{
    IX_HSSACC_FRM_SYNC_INPUT,          /**< Frame sync is sampled as an input */
    IX_HSSACC_FRM_SYNC_INVALID_VALUE,  /**< 1 is not used */
    IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated 
					  off a falling clock edge */
    IX_HSSACC_FRM_SYNC_OUTPUT_RISING,  /**< Frame sync is an output generated 
					  off a rising clock edge */
    IX_HSSACC_FRM_SYNC_ENABLE_MAX      /**< Delimiter for error checks */
} IxHssAccFrmSyncEnable;

/**
 * @enum IxHssAccClkEdge
 * @brief IxHssAccClkEdge is used to determine the clk edge to use for 
 * framing and data
 *
 */
typedef enum
{
    IX_HSSACC_CLK_EDGE_FALLING,  /**< Clock sampled off a falling edge */
    IX_HSSACC_CLK_EDGE_RISING,   /**< Clock sampled off a rising edge */
    IX_HSSACC_CLK_EDGE_MAX       /**< Delimiter for error checks */
} IxHssAccClkEdge;

/**
 * @enum IxHssAccClkDir
 * @brief The HSS clock direction
 *
 */
typedef enum
{
    IX_HSSACC_SYNC_CLK_DIR_INPUT,    /**< Clock is an input */
    IX_HSSACC_SYNC_CLK_DIR_OUTPUT,   /**< Clock is an output */
    IX_HSSACC_SYNC_CLK_DIR_MAX       /**< Delimiter for error checks */
} IxHssAccClkDir;

/**
 * @enum IxHssAccFrmPulseUsage
 * @brief The HSS frame pulse usage
 *
 */
typedef enum
{
    IX_HSSACC_FRM_PULSE_ENABLED,     /**< Generate/Receive frame pulses */
    IX_HSSACC_FRM_PULSE_DISABLED,    /**< Disregard frame pulses */
    IX_HSSACC_FRM_PULSE_MAX          /**< Delimiter for error checks */
} IxHssAccFrmPulseUsage;

/**
 * @enum IxHssAccDataRate
 * @brief The HSS Data rate in relation to the clock