stx7200.c

u-boot 源代码

	writel(0x00000046, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000047, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004E, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004F, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO IDLE MODE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO SHIFT DR STATE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SHIFT DATA IN TDO */
	for (i = 0; i <= 366; i++)
	{
		writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
		writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
		USB_tdo = readl(STX7200_SYSCONF_SYS_CFG00);
	}

	for (j = 0; j < 2; j++)
	{
		for (i = 0; i <= 365; i++)
		{
			if ((i == 71) || (i == 192) || (i == 313))
			{
				writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
				writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
			}
			writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
			writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
			if ((i == 365))
			{
				writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
				writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
			}
		}
	}

	for (i = 0; i <= 366; i++)
	{
		writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
		writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
		USB_tdo = readl(STX7200_SYSCONF_SYS_CFG00);
	}

	/* SET TAP INTO IDLE MODE */
	writel(0x0000004C, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004D, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004C, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004D, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO SHIFT IR STATE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SHIFT DATA IN TDI = 101 select TCB */
	writel(0x00000046, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000047, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004E, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004F, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO IDLE MODE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO SHIFT DR STATE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SHIFT DATA IN TCB */
	for (i = 0; i <= 53; i++)
	{
		if ((i == 0) || (i == 1) || (i == 18) || (i == 19)
		    || (i == 36) || (i == 37))
		{
			writel(0x00000046, STX7200_SYSCONF_SYS_CFG33);
			writel(0x00000047, STX7200_SYSCONF_SYS_CFG33);
		}
		if ((i == 53))
		{
			writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
			writel(0x0000004D, STX7200_SYSCONF_SYS_CFG33);
		}
		writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
		writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	}

	/* SET TAP INTO IDLE MODE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	for (i = 0; i <= 53; i++)
	{
		writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
		writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
		USB_tdo = readl(STX7200_SYSCONF_SYS_CFG00);
	}

	/* SET TAP INTO SHIFT IR STATE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SHIFT DATA IN TDI = 110 select TPR */
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000046, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000047, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004E, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004F, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO IDLE MODE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* SET TAP INTO SHIFT DR STATE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	for (i = 0; i <= 366; i++)
	{
		writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
		writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);
		USB_tdo = readl(STX7200_SYSCONF_SYS_CFG00);
	}

	/* SET TAP INTO IDLE MODE */
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004c, STX7200_SYSCONF_SYS_CFG33);
	writel(0x0000004d, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000044, STX7200_SYSCONF_SYS_CFG33);
	writel(0x00000045, STX7200_SYSCONF_SYS_CFG33);

	/* 20ms delay */
	udelay(20000);

	/* ENABLE SOFT JTAG */
	writel(0x00000040, STX7200_SYSCONF_SYS_CFG33);
}
#endif	/* CONFIG_USB_STI7200_CUT1_SOFT_JTAG_RESET_WORKAROUND */

extern void stx7200_usb_init(void)
{
	DECLARE_GLOBAL_DATA_PTR;
	const bd_t * const bd = gd->bd;
	unsigned long reg;
	const unsigned char power_pins[3] = {1, 3, 4};
	const unsigned char oc_pins[3] = {0, 2, 5};
#if CFG_USB_BASE == CFG_USB0_BASE
	const size_t port = 0;
#elif CFG_USB_BASE == CFG_USB1_BASE
	const size_t port = 1;
#elif CFG_USB_BASE == CFG_USB2_BASE
	const size_t port = 2;
#else
#error Unknown USB Host Controller Base Address
#endif

	/* ClockgenB powers up with all the frequency synths bypassed.
	 * Enable them all here.  Without this, USB 1.1 doesn't work,
	 * as it needs a 48MHz clock which is separate from the USB 2
	 * clock which is derived from the SATA clock. */
	writel(0, STX7200_CLOCKGENB_OUT_MUX_CFG);

	/* route USB and parts of MAFE instead of DVO.*/
	/* DVO output selection (probably ignored). */
	reg = readl(STX7200_SYSCONF_SYS_CFG07);
	reg &= ~(1ul<<26); /* conf_pad_pio[2] = 0 */
	reg &= ~(1ul<<27); /* conf_pad_pio[3] = 0 */
	writel(reg, STX7200_SYSCONF_SYS_CFG07);

	/* Enable soft JTAG mode for USB and SATA */
	reg = readl(STX7200_SYSCONF_SYS_CFG33);
	reg |= (1ul<<6);    /* soft_jtag_en = 1 */
	reg &= ~(0xful<<0); /* tck = tdi = trstn_usb = tms_usb = 0 */
	writel(reg, STX7200_SYSCONF_SYS_CFG33);

#ifdef CONFIG_USB_STI7200_CUT1_SOFT_JTAG_RESET_WORKAROUND
	/* reset USB HC via the JTAG scan path */
	usb_soft_jtag_reset();
#endif

	/* USB power */
	SET_PIO_PIN(PIO_PORT(7), power_pins[port], STPIO_ALT_OUT);
	STPIO_SET_PIN(PIO_PORT(7), power_pins[port], 1);

	/* USB Over-Current */
 	if (STX7200_DEVICEID_CUT(bd->bi_devid) < 2)
		SET_PIO_PIN(PIO_PORT(7), oc_pins[port], STPIO_ALT_BIDIR);
	else
		SET_PIO_PIN(PIO_PORT(7), oc_pins[port], STPIO_IN);

	/* tusb_powerdown_req[port] = 0 */
	reg = readl(STX7200_SYSCONF_SYS_CFG22);
	reg &= ~(1ul<<(port+3));
	writel(reg, STX7200_SYSCONF_SYS_CFG22);

	/* Set strap mode */
#define STRAP_MODE	AHB2STBUS_STRAP_16_BIT
	reg = readl(AHB2STBUS_STRAP);
#if STRAP_MODE == 0
	reg &= ~AHB2STBUS_STRAP_16_BIT;
#else
	reg |= STRAP_MODE;
#endif
	writel(reg, AHB2STBUS_STRAP);

	/* Start PLL */
	reg = readl(AHB2STBUS_STRAP);
	writel(reg | AHB2STBUS_STRAP_PLL, AHB2STBUS_STRAP);
	udelay(100000);	/* QQQ: can this delay be shorter ? */
	writel(reg & (~AHB2STBUS_STRAP_PLL), AHB2STBUS_STRAP);
	udelay(100000);	/* QQQ: can this delay be shorter ? */

	/* Set the STBus Opcode Config for 32-bit access */
	writel(AHB2STBUS_STBUS_OPC_32BIT, AHB2STBUS_STBUS_OPC);

	/* Set the Message Size Config to 4 packets per message */
	writel(AHB2STBUS_MSGSIZE_4, AHB2STBUS_MSGSIZE);

	/* Set the Chunk Size Config to 4 packets per chunk */
	writel(AHB2STBUS_CHUNKSIZE_4, AHB2STBUS_CHUNKSIZE);
}

#endif /* defined(CONFIG_USB_OHCI_NEW) */