defbf532.h

u-boot 源代码

#define DI_EN_P			7	/* Data Interrupt Enable */

/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
#define DMA_DONE		0x00000001	/* DMA Done Indicator */
#define DMA_ERR			0x00000002	/* DMA Error Indicator */
#define DFETCH			0x00000004	/* Descriptor Fetch Indicator */
#define DMA_RUN			0x00000008	/* DMA Running Indicator */

#define DMA_DONE_P		0	/* DMA Done Indicator */
#define DMA_ERR_P		1	/* DMA Error Indicator */
#define DFETCH_P		2	/* Descriptor Fetch Indicator */
#define DMA_RUN_P		3	/* DMA Running Indicator */

/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
#define CTYPE			0x00000040	/* DMA Channel Type Indicator */
#define CTYPE_P			6	/* DMA Channel Type Indicator BIT POSITION */
#define PCAP8			0x00000080	/* DMA 8-bit Operation Indicator */
#define PCAP16			0x00000100	/* DMA 16-bit Operation Indicator */
#define PCAP32			0x00000200	/* DMA 32-bit Operation Indicator */
#define PCAPWR			0x00000400	/* DMA Write Operation Indicator */
#define PCAPRD			0x00000800	/* DMA Read Operation Indicator */
#define PMAP			0x00007000	/* DMA Peripheral Map Field */

/*
 * GENERAL PURPOSE TIMER MASKS
 */

/* PWM Timer bit definitions */

/* TIMER_ENABLE Register */
#define TIMEN0			0x0001
#define TIMEN1			0x0002
#define TIMEN2			0x0004

#define TIMEN0_P		0x00
#define TIMEN1_P		0x01
#define TIMEN2_P		0x02

/* TIMER_DISABLE Register */
#define TIMDIS0			0x0001
#define TIMDIS1			0x0002
#define TIMDIS2			0x0004

#define TIMDIS0_P		0x00
#define TIMDIS1_P		0x01
#define TIMDIS2_P		0x02

/* TIMER_STATUS Register */
#define TIMIL0			0x0001
#define TIMIL1			0x0002
#define TIMIL2			0x0004
#define TOVL_ERR0		0x0010
#define TOVL_ERR1		0x0020
#define TOVL_ERR2		0x0040
#define TRUN0			0x1000
#define TRUN1			0x2000
#define TRUN2			0x4000

#define TIMIL0_P		0x00
#define TIMIL1_P		0x01
#define TIMIL2_P		0x02
#define TOVL_ERR0_P		0x04
#define TOVL_ERR1_P		0x05
#define TOVL_ERR2_P		0x06
#define TRUN0_P			0x0C
#define TRUN1_P			0x0D
#define TRUN2_P			0x0E

/* TIMERx_CONFIG Registers */
#define PWM_OUT			0x0001
#define WDTH_CAP		0x0002
#define EXT_CLK			0x0003
#define PULSE_HI		0x0004
#define PERIOD_CNT		0x0008
#define IRQ_ENA			0x0010
#define TIN_SEL			0x0020
#define OUT_DIS			0x0040
#define CLK_SEL			0x0080
#define TOGGLE_HI		0x0100
#define EMU_RUN			0x0200
#define ERR_TYP(x)		((x & 0x03) << 14)

#define TMODE_P0		0x00
#define TMODE_P1		0x01
#define PULSE_HI_P		0x02
#define PERIOD_CNT_P		0x03
#define IRQ_ENA_P		0x04
#define TIN_SEL_P		0x05
#define OUT_DIS_P		0x06
#define CLK_SEL_P		0x07
#define TOGGLE_HI_P		0x08
#define EMU_RUN_P		0x09
#define ERR_TYP_P0		0x0E
#define ERR_TYP_P1		0x0F

/*
 * PROGRAMMABLE FLAG MASKS
 */

/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
#define PF0			0x0001
#define PF1			0x0002
#define PF2			0x0004
#define PF3			0x0008
#define PF4			0x0010
#define PF5			0x0020
#define PF6			0x0040
#define PF7			0x0080
#define PF8			0x0100
#define PF9			0x0200
#define PF10			0x0400
#define PF11			0x0800
#define PF12			0x1000
#define PF13			0x2000
#define PF14			0x4000
#define PF15			0x8000

/* General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
#define PF0_P			0
#define PF1_P			1
#define PF2_P			2
#define PF3_P			3
#define PF4_P			4
#define PF5_P			5
#define PF6_P			6
#define PF7_P			7
#define PF8_P			8
#define PF9_P			9
#define PF10_P			10
#define PF11_P			11
#define PF12_P			12
#define PF13_P			13
#define PF14_P			14
#define PF15_P			15

/*
 * SERIAL PERIPHERAL INTERFACE (SPI) MASKS
 */

/* SPI_CTL Masks */
#define TIMOD			0x00000003	/* Transfer initiation mode and interrupt generation */
#define SZ			0x00000004	/* Send Zero (=0) or last (=1) word when TDBR empty. */
#define GM			0x00000008	/* When RDBR full, get more (=1) data or discard (=0) incoming Data */
#define PSSE			0x00000010	/* Enable (=1) Slave-Select input for Master. */
#define EMISO			0x00000020	/* Enable (=1) MISO pin as an output. */
#define SIZE			0x00000100	/* Word length (0 => 8 bits, 1 => 16 bits) */
#define LSBF			0x00000200	/* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
#define CPHA			0x00000400	/* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
#define CPOL			0x00000800	/* Clock polarity (0 => active-high, 1 => active-low) */
#define MSTR			0x00001000	/* Configures SPI as master (=1) or slave (=0) */
#define WOM			0x00002000	/* Open drain (=1) data output enable (for MOSI and MISO) */
#define SPE			0x00004000	/* SPI module enable (=1), disable (=0) */

/* SPI_FLG Masks */
#define FLS1			0x00000002	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2			0x00000004	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3			0x00000008	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4			0x00000010	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5			0x00000020	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6			0x00000040	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7			0x00000080	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1			0x00000200	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2			0x00000400	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3			0x00000800	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4			0x00001000	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5			0x00002000	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6			0x00004000	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7			0x00008000	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */

/* SPI_FLG Bit Positions */
#define FLS1_P			0x00000001	/* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLS2_P			0x00000002	/* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLS3_P			0x00000003	/* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLS4_P			0x00000004	/* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLS5_P			0x00000005	/* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLS6_P			0x00000006	/* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLS7_P			0x00000007	/* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
#define FLG1_P			0x00000009	/* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
#define FLG2_P			0x0000000A	/* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
#define FLG3_P			0x0000000B	/* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
#define FLG4_P			0x0000000C	/* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
#define FLG5_P			0x0000000D	/* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
#define FLG6_P			0x0000000E	/* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
#define FLG7_P			0x0000000F	/* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */

/* SPI_STAT Masks */
#define SPIF			0x00000001	/* Set (=1) when SPI single-word transfer complete */
#define MODF			0x00000002	/* Set(=1)in a master device when some other device tries to become master */
#define TXE			0x00000004	/* Set (=1) when transmission occurs with no new data in SPI_TDBR */
#define TXS			0x00000008	/* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
#define RBSY			0x00000010	/* Set (=1) when data is received with RDBR full */
#define RXS			0x00000020	/* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
#define TXCOL			0x00000040	/* When set (=1), corrupt data may have been transmitted */

/*
 * ASYNCHRONOUS MEMORY CONTROLLER MASKS
 */

/* AMGCTL Masks */
#define AMCKEN			0x00000001	/* Enable CLKOUT */
#define AMBEN_B0		0x00000002	/* Enable Asynchronous Memory Bank 0 only */
#define AMBEN_B0_B1		0x00000004	/* Enable Asynchronous Memory Banks 0 & 1 only */
#define AMBEN_B0_B1_B2		0x00000006	/* Enable Asynchronous Memory Banks 0, 1, and 2 */
#define AMBEN_ALL		0x00000008	/* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */

/* AMGCTL Bit Positions */
#define AMCKEN_P		0x00000000	/* Enable CLKOUT */
#define AMBEN_P0		0x00000001	/* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
#define AMBEN_P1		0x00000002	/* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
#define AMBEN_P2		0x00000003	/* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */

/* AMBCTL0 Masks */
#define B0RDYEN			0x00000001	/* Bank 0 RDY Enable, 0=disable, 1=enable */
#define B0RDYPOL		0x00000002	/* Bank 0 RDY Active high, 0=active low, 1=active high */
#define B0TT_1			0x00000004	/* Bank 0 Transition Time from Read to Write = 1 cycle */
#define B0TT_2			0x00000008	/* Bank 0 Transition Time from Read to Write = 2 cycles */
#define B0TT_3			0x0000000C	/* Bank 0 Transition Time from Read to Write = 3 cycles */
#define B0TT_4			0x00000000	/* Bank 0 Transition Time from Read to Write = 4 cycles */
#define B0ST_1			0x00000010	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
#define B0ST_2			0x00000020	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
#define B0ST_3			0x00000030	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
#define B0ST_4			0x00000000	/* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
#define B0HT_1			0x00000040	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
#define B0HT_2			0x00000080	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
#define B0HT_3			0x000000C0	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
#define B0HT_0			0x00000000	/* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
#define B0RAT_1			0x00000100	/* Bank 0 Read Access Time = 1 cycle */
#define B0RAT_2			0x00000200	/* Bank 0 Read Access Time = 2 cycles */
#define B0RAT_3			0x00000300	/* Bank 0 Read Access Time = 3 cycles */
#define B0RAT_4			0x00000400	/* Bank 0 Read Access Time = 4 cycles */
#define B0RAT_5			0x00000500	/* Bank 0 Read Access Time = 5 cycles */
#define B0RAT_6			0x00000600	/* Bank 0 Read Access Time = 6 cycles */