defbf532.h

u-boot 源代码

/*
 * defBF532.h
 *
 * This file is subject to the terms and conditions of the GNU Public
 * License. See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Non-GPL License also available as part of VisualDSP++
 *
 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
 *
 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
 *
 * This file under source code control, please send bugs or changes to:
 * [e-mail]
 *
 */

/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */

#ifndef _DEF_BF532_H
#define _DEF_BF532_H

/*
 * #if !defined(__ADSPLPBLACKFIN__)
 * #warning defBF532.h should only be included for 532 compatible chips
 * #endif
 */

/* include all Core registers and bit definitions */
#include <asm/arch-common/def_LPBlackfin.h>

/* Helper macros
 * usage:
 *  P0.H = HI(UART_THR);
 *  P0.L = LO(UART_THR);
 */

#define LO(con32)		((con32) & 0xFFFF)
#define lo(con32)		((con32) & 0xFFFF)
#define HI(con32)		(((con32) >> 16) & 0xFFFF)
#define hi(con32)		(((con32) >> 16) & 0xFFFF)

/*
 * System MMR Register Map
 */

/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define PLL_CTL			0xFFC00000	/* PLL Control register (16-bit) */
#define PLL_DIV			0xFFC00004	/* PLL Divide Register (16-bit) */
#define VR_CTL			0xFFC00008	/* Voltage Regulator Control Register (16-bit) */
#define PLL_STAT		0xFFC0000C	/* PLL Status register (16-bit) */
#define PLL_LOCKCNT		0xFFC00010	/* PLL Lock Count register (16-bit) */
#define	CHIPID			0xFFC00014	/* Chip ID register (32-bit)    */
#define SWRST			0xFFC00100	/* Software Reset Register (16-bit) */
#define SYSCR			0xFFC00104	/* System Configuration register */

/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
#define SIC_RVECT		0xFFC00108	/* Interrupt Reset Vector Address Register */
#define SIC_IMASK		0xFFC0010C	/* Interrupt Mask Register */
#define SIC_IAR0		0xFFC00110	/* Interrupt Assignment Register 0 */
#define SIC_IAR1		0xFFC00114	/* Interrupt Assignment Register 1 */
#define SIC_IAR2		0xFFC00118	/* Interrupt Assignment Register 2 */
#define SIC_ISR			0xFFC00120	/* Interrupt Status Register */
#define SIC_IWR			0xFFC00124	/* Interrupt Wakeup Register */

/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
#define WDOG_CTL		0xFFC00200	/* Watchdog Control Register */
#define WDOG_CNT		0xFFC00204	/* Watchdog Count Register */
#define WDOG_STAT		0xFFC00208	/* Watchdog Status Register */

/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
#define RTC_STAT		0xFFC00300	/* RTC Status Register */
#define RTC_ICTL		0xFFC00304	/* RTC Interrupt Control Register */
#define RTC_ISTAT		0xFFC00308	/* RTC Interrupt Status Register */
#define RTC_SWCNT		0xFFC0030C	/* RTC Stopwatch Count Register */
#define RTC_ALARM		0xFFC00310	/* RTC Alarm Time Register */
#define RTC_FAST		0xFFC00314	/* RTC Prescaler Enable Register */
#define RTC_PREN		0xFFC00314	/* RTC Prescaler Enable Register (alternate macro) */

/* UART Controller (0xFFC00400 - 0xFFC004FF) */
#define UART_THR		0xFFC00400	/* Transmit Holding register */
#define UART_RBR		0xFFC00400	/* Receive Buffer register */
#define UART_DLL		0xFFC00400	/* Divisor Latch (Low-Byte) */
#define UART_IER		0xFFC00404	/* Interrupt Enable Register */
#define UART_DLH		0xFFC00404	/* Divisor Latch (High-Byte) */
#define UART_IIR		0xFFC00408	/* Interrupt Identification Register */
#define UART_LCR		0xFFC0040C	/* Line Control Register */
#define UART_MCR		0xFFC00410	/* Modem Control Register */
#define UART_LSR		0xFFC00414	/* Line Status Register */
/* #define UART_MSR 0xFFC00418 */		/* Modem Status Register (UNUSED in ADSP-BF532) */
#define UART_SCR		0xFFC0041C	/* SCR Scratch Register */
#define UART_GCTL		0xFFC00424	/* Global Control Register */

/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI_CTL			0xFFC00500	/* SPI Control Register */
#define SPI_FLG			0xFFC00504	/* SPI Flag register */
#define SPI_STAT		0xFFC00508	/* SPI Status register */
#define SPI_TDBR		0xFFC0050C	/* SPI Transmit Data Buffer Register */
#define SPI_RDBR		0xFFC00510	/* SPI Receive Data Buffer Register */
#define SPI_BAUD		0xFFC00514	/* SPI Baud rate Register */
#define SPI_SHADOW		0xFFC00518	/* SPI_RDBR Shadow Register */

/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
#define TIMER0_CONFIG		0xFFC00600	/* Timer 0 Configuration Register */
#define TIMER0_COUNTER		0xFFC00604	/* Timer 0 Counter Register */
#define TIMER0_PERIOD		0xFFC00608	/* Timer 0 Period Register */
#define TIMER0_WIDTH		0xFFC0060C	/* Timer 0 Width Register */

#define TIMER1_CONFIG		0xFFC00610	/*  Timer 1 Configuration Register */
#define TIMER1_COUNTER		0xFFC00614	/*  Timer 1 Counter Register */
#define TIMER1_PERIOD		0xFFC00618	/*  Timer 1 Period Register */
#define TIMER1_WIDTH		0xFFC0061C	/*  Timer 1 Width Register */

#define TIMER2_CONFIG		0xFFC00620	/* Timer 2 Configuration Register */
#define TIMER2_COUNTER		0xFFC00624	/* Timer 2 Counter Register */
#define TIMER2_PERIOD		0xFFC00628	/* Timer 2 Period Register */
#define TIMER2_WIDTH		0xFFC0062C	/* Timer 2 Width Register */

#define TIMER_ENABLE		0xFFC00640	/* Timer Enable Register */
#define TIMER_DISABLE		0xFFC00644	/* Timer Disable Register */
#define TIMER_STATUS		0xFFC00648	/* Timer Status Register */

/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
#define FIO_FLAG_D		0xFFC00700	/* Flag Mask to directly specify state of pins */
#define FIO_FLAG_C		0xFFC00704	/* Peripheral Interrupt Flag Register (clear) */
#define FIO_FLAG_S		0xFFC00708	/* Peripheral Interrupt Flag Register (set) */
#define FIO_FLAG_T		0xFFC0070C	/* Flag Mask to directly toggle state of pins */
#define FIO_MASKA_D		0xFFC00710	/* Flag Mask Interrupt A Register (set directly) */
#define FIO_MASKA_C		0xFFC00714	/* Flag Mask Interrupt A Register (clear) */
#define FIO_MASKA_S		0xFFC00718	/* Flag Mask Interrupt A Register (set) */
#define FIO_MASKA_T		0xFFC0071C	/* Flag Mask Interrupt A Register (toggle) */
#define FIO_MASKB_D		0xFFC00720	/* Flag Mask Interrupt B Register (set directly) */
#define FIO_MASKB_C		0xFFC00724	/* Flag Mask Interrupt B Register (clear) */
#define FIO_MASKB_S		0xFFC00728	/* Flag Mask Interrupt B Register (set) */
#define FIO_MASKB_T		0xFFC0072C	/* Flag Mask Interrupt B Register (toggle) */
#define FIO_DIR			0xFFC00730	/* Peripheral Flag Direction Register */
#define FIO_POLAR		0xFFC00734	/* Flag Source Polarity Register */
#define FIO_EDGE		0xFFC00738	/* Flag Source Sensitivity Register */
#define FIO_BOTH		0xFFC0073C	/* Flag Set on BOTH Edges Register */
#define FIO_INEN		0xFFC00740	/* Flag Input Enable Register */

/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
#define SPORT0_TCR1		0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2		0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider */
#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
#define SPORT0_TX		0xFFC00810	/* SPORT0 TX Data Register */
#define SPORT0_RX		0xFFC00818	/* SPORT0 RX Data Register */
#define SPORT0_RCR1		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_RCR2		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider */
#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
#define SPORT0_STAT		0xFFC00830	/* SPORT0 Status Register */
#define SPORT0_CHNL		0xFFC00834	/* SPORT0 Current Channel Register */
#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */

/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
#define SPORT1_TCR1		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_TCR2		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider */
#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
#define SPORT1_TX		0xFFC00910	/* SPORT1 TX Data Register */
#define SPORT1_RX		0xFFC00918	/* SPORT1 RX Data Register */
#define SPORT1_RCR1		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_RCR2		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider */
#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
#define SPORT1_STAT		0xFFC00930	/* SPORT1 Status Register */
#define SPORT1_CHNL		0xFFC00934	/* SPORT1 Current Channel Register */
#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */

/* Asynchronous Memory Controller - External Bus Interface Unit */
#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */
#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */

/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */
#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */
#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */
#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register */

/* DMA Test Registers */
#define DMA_CCOMP		0xFFC00B04	/* DMA Cycle Count Register */
#define DMA_ACOMP		0xFFC00B00	/* Debug Compare Address Register */
#define DMA_MISR		0xFFC00B08	/* MISR Register */
#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */
#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register */
#define DMA_TMODE		0xFFC00B14	/* DMA Test Modes Register */
#define DMA_TMCHAN		0xFFC00B18	/* DMA Testmode Selected Channel Register */
#define DMA_TMSTAT		0xFFC00B1C	/* DMA Testmode Channel Status Register */
#define DMA_TMBD		0xFFC00B20	/* DMA Testmode DAB Bus Data Register */
#define DMA_TMM0D		0xFFC00B24	/* DMA Testmode Mem0 Data Register */
#define DMA_TMM1D		0xFFC00B28	/* DMA Testmode Mem1 Data Register */
#define DMA_TMMA		0xFFC00B2C	/* DMA Testmode Memory Address Register */

/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
#define DMA0_CONFIG		0xFFC00C08	/* DMA Channel 0 Configuration Register */
#define DMA0_NEXT_DESC_PTR	0xFFC00C00	/* DMA Channel 0 Next Descriptor Pointer Register */
#define DMA0_START_ADDR		0xFFC00C04	/* DMA Channel 0 Start Address Register */
#define DMA0_X_COUNT		0xFFC00C10	/* DMA Channel 0 X Count Register */
#define DMA0_Y_COUNT		0xFFC00C18	/* DMA Channel 0 Y Count Register */
#define DMA0_X_MODIFY		0xFFC00C14	/* DMA Channel 0 X Modify Register */
#define DMA0_Y_MODIFY		0xFFC00C1C	/* DMA Channel 0 Y Modify Register */
#define DMA0_CURR_DESC_PTR	0xFFC00C20	/* DMA Channel 0 Current Descriptor Pointer Register */
#define DMA0_CURR_ADDR		0xFFC00C24	/* DMA Channel 0 Current Address Register */
#define DMA0_CURR_X_COUNT	0xFFC00C30	/* DMA Channel 0 Current X Count Register */
#define DMA0_CURR_Y_COUNT	0xFFC00C38	/* DMA Channel 0 Current Y Count Register */
#define DMA0_IRQ_STATUS		0xFFC00C28	/* DMA Channel 0 Interrupt/Status Register */
#define DMA0_PERIPHERAL_MAP	0xFFC00C2C	/* DMA Channel 0 Peripheral Map Register */

#define DMA1_CONFIG		0xFFC00C48	/* DMA Channel 1 Configuration Register */
#define DMA1_NEXT_DESC_PTR	0xFFC00C40	/* DMA Channel 1 Next Descriptor Pointer Register */