pxa-regs.h

u-boot 源代码

#define GPIO27		__REG(0x40e10400)
#define GPIO28		__REG(0x40e10404)
#define GPIO29		__REG(0x40e10408)
#define GPIO30		__REG(0x40e1040c)
#define GPIO31		__REG(0x40e10410)
#define GPIO32		__REG(0x40e10414)
#define GPIO33		__REG(0x40e10418)
#define GPIO34		__REG(0x40e1041c)
#define GPIO35		__REG(0x40e10420)
#define GPIO36		__REG(0x40e10424)
#define GPIO37		__REG(0x40e10428)
#define GPIO38		__REG(0x40e1042c)
#define GPIO39		__REG(0x40e10430)
#define GPIO40		__REG(0x40e10434)
#define GPIO41		__REG(0x40e10438)
#define GPIO42		__REG(0x40e1043c)
#define GPIO43		__REG(0x40e10440)
#define GPIO44		__REG(0x40e10444)
#define GPIO45		__REG(0x40e10448)
#define GPIO46		__REG(0x40e1044c)
#define GPIO47		__REG(0x40e10450)
#define GPIO48		__REG(0x40e10454)

#define GPIO10		__REG(0x40e10458)

#define GPIO49		__REG(0x40e1045c)
#define GPIO50		__REG(0x40e10460)
#define GPIO51		__REG(0x40e10464)
#define GPIO52		__REG(0x40e10468)
#define GPIO53		__REG(0x40e1046c)
#define GPIO54		__REG(0x40e10470)
#define GPIO55		__REG(0x40e10474)
#define GPIO56		__REG(0x40e10478)
#define GPIO57		__REG(0x40e1047c)
#define GPIO58		__REG(0x40e10480)
#define GPIO59		__REG(0x40e10484)
#define GPIO60		__REG(0x40e10488)
#define GPIO61		__REG(0x40e1048c)
#define GPIO62		__REG(0x40e10490)

#define GPIO6_2		__REG(0x40e10494)
#define GPIO7_2		__REG(0x40e10498)
#define GPIO8_2		__REG(0x40e1049c)
#define GPIO9_2		__REG(0x40e104a0)
#define GPIO10_2	__REG(0x40e104a4)
#define GPIO11_2	__REG(0x40e104a8)
#define GPIO12_2	__REG(0x40e104ac)
#define GPIO13_2	__REG(0x40e104b0)

#define GPIO63		__REG(0x40e104b4)
#define GPIO64		__REG(0x40e104b8)
#define GPIO65		__REG(0x40e104bc)
#define GPIO66		__REG(0x40e104c0)
#define GPIO67		__REG(0x40e104c4)
#define GPIO68		__REG(0x40e104c8)
#define GPIO69		__REG(0x40e104cc)
#define GPIO70		__REG(0x40e104d0)
#define GPIO71		__REG(0x40e104d4)
#define GPIO72		__REG(0x40e104d8)
#define GPIO73		__REG(0x40e104dc)

#define GPIO14_2	__REG(0x40e104e0)
#define GPIO15_2	__REG(0x40e104e4)
#define GPIO16_2	__REG(0x40e104e8)
#define GPIO17_2	__REG(0x40e104ec)

#define GPIO74		__REG(0x40e104f0)
#define GPIO75		__REG(0x40e104f4)
#define GPIO76		__REG(0x40e104f8)
#define GPIO77		__REG(0x40e104fc)
#define GPIO78		__REG(0x40e10500)
#define GPIO79		__REG(0x40e10504)
#define GPIO80		__REG(0x40e10508)
#define GPIO81		__REG(0x40e1050c)
#define GPIO82		__REG(0x40e10510)
#define GPIO83		__REG(0x40e10514)
#define GPIO84		__REG(0x40e10518)
#define GPIO85		__REG(0x40e1051c)
#define GPIO86		__REG(0x40e10520)
#define GPIO87		__REG(0x40e10524)
#define GPIO88		__REG(0x40e10528)
#define GPIO89		__REG(0x40e1052c)
#define GPIO90		__REG(0x40e10530)
#define GPIO91		__REG(0x40e10534)
#define GPIO92		__REG(0x40e10538)
#define GPIO93		__REG(0x40e1053c)
#define GPIO94		__REG(0x40e10540)
#define GPIO95		__REG(0x40e10544)
#define GPIO96		__REG(0x40e10548)
#define GPIO97		__REG(0x40e1054c)
#define GPIO98		__REG(0x40e10550)

#define GPIO99		__REG(0x40e10600)
#define GPIO100		__REG(0x40e10604)
#define GPIO101		__REG(0x40e10608)
#define GPIO102		__REG(0x40e1060c)
#define GPIO103		__REG(0x40e10610)
#define GPIO104		__REG(0x40e10614)
#define GPIO105		__REG(0x40e10618)
#define GPIO106		__REG(0x40e1061c)
#define GPIO107		__REG(0x40e10620)
#define GPIO108		__REG(0x40e10624)
#define GPIO109		__REG(0x40e10628)
#define GPIO110		__REG(0x40e1062c)
#define GPIO111		__REG(0x40e10630)
#define GPIO112		__REG(0x40e10634)

#define GPIO113		__REG(0x40e10638)
#define GPIO114		__REG(0x40e1063c)
#define GPIO115		__REG(0x40e10640)
#define GPIO116		__REG(0x40e10644)
#define GPIO117		__REG(0x40e10648)
#define GPIO118		__REG(0x40e1064c)
#define GPIO119		__REG(0x40e10650)
#define GPIO120		__REG(0x40e10654)
#define GPIO121		__REG(0x40e10658)
#define GPIO122		__REG(0x40e1065c)
#define GPIO123		__REG(0x40e10660)
#define GPIO124		__REG(0x40e10664)
#define GPIO125		__REG(0x40e10668)
#define GPIO126		__REG(0x40e1066c)
#define GPIO127		__REG(0x40e10670)

#define GPIO0_2		__REG(0x40e10674)
#define GPIO1_2		__REG(0x40e10678)
#define GPIO2_2		__REG(0x40e1067c)
#define GPIO3_2		__REG(0x40e10680)
#define GPIO4_2		__REG(0x40e10684)
#define GPIO5_2		__REG(0x40e10688)

/* MFPR Bit Definitions, see 4-10, Vol. 1 */
#define PULL_SEL	0x8000
#define PULLUP_EN	0x4000
#define PULLDOWN_EN	0x2000

#define DRIVE_FAST_1mA	0x0
#define DRIVE_FAST_2mA	0x400
#define DRIVE_FAST_3mA	0x800
#define DRIVE_FAST_4mA	0xC00
#define DRIVE_SLOW_6mA	0x1000
#define DRIVE_FAST_6mA	0x1400
#define DRIVE_SLOW_10mA	0x1800
#define DRIVE_FAST_10mA	0x1C00

#define SLEEP_SEL	0x200
#define SLEEP_DATA	0x100
#define SLEEP_OE_N	0x80
#define EDGE_CLEAR	0x40
#define EDGE_FALL_EN	0x20
#define EDGE_RISE_EN	0x10

#define AF_SEL_0	0x0	/* Alternate function 0 (reset state) */
#define AF_SEL_1	0x1	/* Alternate function 1 */
#define AF_SEL_2	0x2	/* Alternate function 2 */
#define AF_SEL_3	0x3	/* Alternate function 3 */
#define AF_SEL_4	0x4	/* Alternate function 4 */
#define AF_SEL_5	0x5	/* Alternate function 5 */
#define AF_SEL_6	0x6	/* Alternate function 6 */
#define AF_SEL_7	0x7	/* Alternate function 7 */


#else /* CONFIG_CPU_MONAHANS */

#define GAFR0_L		__REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
#define GAFR0_U		__REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
#define GAFR1_L		__REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
#define GAFR1_U		__REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
#define GAFR2_L		__REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
#define GAFR2_U		__REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO 80 */
#endif /* CONFIG_CPU_MONAHANS */

/* More handy macros.  The argument is a literal GPIO number. */

#define GPIO_bit(x)	(1 << ((x) & 0x1f))

#ifdef CONFIG_PXA27X

/* Interrupt Controller */

#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */

#define _GPLR(x)	__REG2(0x40E00000, ((x) & 0x60) >> 3)
#define _GPDR(x)	__REG2(0x40E0000C, ((x) & 0x60) >> 3)
#define _GPSR(x)	__REG2(0x40E00018, ((x) & 0x60) >> 3)
#define _GPCR(x)	__REG2(0x40E00024, ((x) & 0x60) >> 3)
#define _GRER(x)	__REG2(0x40E00030, ((x) & 0x60) >> 3)
#define _GFER(x)	__REG2(0x40E0003C, ((x) & 0x60) >> 3)
#define _GEDR(x)	__REG2(0x40E00048, ((x) & 0x60) >> 3)
#define _GAFR(x)	__REG2(0x40E00054, ((x) & 0x70) >> 2)

#define GPLR(x)		__REG2(0x40E00000 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GPDR(x)		__REG2(0x40E0000C + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GPSR(x)		__REG2(0x40E00018 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GPCR(x)		__REG2(0x40E00024 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GRER(x)		__REG2(0x40E00030 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GFER(x)		__REG2(0x40E0003C + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GEDR(x)		__REG2(0x40E00048 + (((x) & 0x7f) < 96) ?  0:0x100, ((x) & 0x60) >> 3)
#define GAFR(x)		__REG2((((x) & 0x7f) < 96) ?  0x40E00054 : \
			 ((((x) & 0x7f) < 112) ? 0x40E0006C : 0x40E00070),((x) & 0x60) >> 3)
#else

#define GPLR(x)		__REG2(0x40E00000, ((x) & 0x60) >> 3)
#define GPDR(x)		__REG2(0x40E0000C, ((x) & 0x60) >> 3)
#define GPSR(x)		__REG2(0x40E00018, ((x) & 0x60) >> 3)
#define GPCR(x)		__REG2(0x40E00024, ((x) & 0x60) >> 3)
#define GRER(x)		__REG2(0x40E00030, ((x) & 0x60) >> 3)
#define GFER(x)		__REG2(0x40E0003C, ((x) & 0x60) >> 3)
#define GEDR(x)		__REG2(0x40E00048, ((x) & 0x60) >> 3)
#define GAFR(x)		__REG2(0x40E00054, ((x) & 0x70) >> 2)

#endif

/* GPIO alternate function assignments */

#define GPIO1_RST		1	/* reset */
#define GPIO6_MMCCLK		6	/* MMC Clock */
#define GPIO8_48MHz		7	/* 48 MHz clock output */
#define GPIO8_MMCCS0		8	/* MMC Chip Select 0 */
#define GPIO9_MMCCS1		9	/* MMC Chip Select 1 */
#define GPIO10_RTCCLK		10	/* real time clock (1 Hz) */
#define GPIO11_3_6MHz		11	/* 3.6 MHz oscillator out */
#define GPIO12_32KHz		12	/* 32 kHz out */
#define GPIO13_MBGNT		13	/* memory controller grant */
#define GPIO14_MBREQ		14	/* alternate bus master request */
#define GPIO15_nCS_1		15	/* chip select 1 */
#define GPIO16_PWM0		16	/* PWM0 output */
#define GPIO17_PWM1		17	/* PWM1 output */
#define GPIO18_RDY		18	/* Ext. Bus Ready */
#define GPIO19_DREQ1		19	/* External DMA Request */
#define GPIO20_DREQ0		20	/* External DMA Request */
#define GPIO23_SCLK		23	/* SSP clock */
#define GPIO24_SFRM		24	/* SSP Frame */
#define GPIO25_STXD		25	/* SSP transmit */
#define GPIO26_SRXD		26	/* SSP receive */
#define GPIO27_SEXTCLK		27	/* SSP ext_clk */
#define GPIO28_BITCLK		28	/* AC97/I2S bit_clk */
#define GPIO29_SDATA_IN		29	/* AC97 Sdata_in0 / I2S Sdata_in */
#define GPIO30_SDATA_OUT	30	/* AC97/I2S Sdata_out */
#define GPIO31_SYNC		31	/* AC97/I2S sync */
#define GPIO32_SDATA_IN1	32	/* AC97 Sdata_in1 */
#define GPIO33_nCS_5		33	/* chip select 5 */
#define GPIO34_FFRXD		34	/* FFUART receive */
#define GPIO34_MMCCS0		34	/* MMC Chip Select 0 */
#define GPIO35_FFCTS		35	/* FFUART Clear to send */
#define GPIO36_FFDCD		36	/* FFUART Data carrier detect */
#define GPIO37_FFDSR		37	/* FFUART data set ready */
#define GPIO38_FFRI		38	/* FFUART Ring Indicator */
#define GPIO39_MMCCS1		39	/* MMC Chip Select 1 */
#define GPIO39_FFTXD		39	/* FFUART transmit data */
#define GPIO40_FFDTR		40	/* FFUART data terminal Ready */
#define GPIO41_FFRTS		41	/* FFUART request to send */
#define GPIO42_BTRXD		42	/* BTUART receive data */
#define GPIO43_BTTXD		43	/* BTUART transmit data */
#define GPIO44_BTCTS		44	/* BTUART clear to send */
#define GPIO45_BTRTS		45	/* BTUART request to send */
#define GPIO46_ICPRXD		46	/* ICP receive data */
#define GPIO46_STRXD		46	/* STD_UART receive data */
#define GPIO47_ICPTXD		47	/* ICP transmit data */
#define GPIO47_STTXD		47	/* STD_UART transmit data */
#define GPIO48_nPOE		48	/* Output Enable for Card Space */
#define GPIO49_nPWE		49	/* Write Enable for Card Space */
#define GPIO50_nPIOR		50	/* I/O Read for Card Space */
#define GPIO51_nPIOW		51	/* I/O Write for Card Space */
#define GPIO52_nPCE_1		52	/* Card Enable for Card Space */
#define GPIO53_nPCE_2		53	/* Card Enable for Card Space */
#define GPIO53_MMCCLK		53	/* MMC Clock */
#define GPIO54_MMCCLK		54	/* MMC Clock */
#define GPIO54_pSKTSEL		54	/* Socket Select for Card Space */
#define GPIO55_nPREG		55	/* Card Addr