pxa-regs.h

u-boot 源代码

#endif

/*
 * Fast Infrared Communication Port
 */
#define ICCR0		__REG(0x40800000)  /* ICP Control Register 0 */
#define ICCR1		__REG(0x40800004)  /* ICP Control Register 1 */
#define ICCR2		__REG(0x40800008)  /* ICP Control Register 2 */
#define ICDR		__REG(0x4080000c)  /* ICP Data Register */
#define ICSR0		__REG(0x40800014)  /* ICP Status Register 0 */
#define ICSR1		__REG(0x40800018)  /* ICP Status Register 1 */

/*
 * Real Time Clock
 */
#define RCNR		__REG(0x40900000)  /* RTC Count Register */
#define RTAR		__REG(0x40900004)  /* RTC Alarm Register */
#define RTSR		__REG(0x40900008)  /* RTC Status Register */
#define RTTR		__REG(0x4090000C)  /* RTC Timer Trim Register */
#define RDAR1		__REG(0x40900018)  /* Wristwatch Day Alarm Reg 1 */
#define RDAR2		__REG(0x40900020)  /* Wristwatch Day Alarm Reg 2 */
#define RYAR1		__REG(0x4090001C)  /* Wristwatch Year Alarm Reg 1 */
#define RYAR2		__REG(0x40900024)  /* Wristwatch Year Alarm Reg 2 */
#define SWAR1		__REG(0x4090002C)  /* Stopwatch Alarm Register 1 */
#define SWAR2		__REG(0x40900030)  /* Stopwatch Alarm Register 2 */
#define PIAR		__REG(0x40900038)  /* Periodic Interrupt Alarm Register */
#define RDCR		__REG(0x40900010)  /* RTC Day Count Register. */
#define RYCR		__REG(0x40900014)  /* RTC Year Count Register. */
#define SWCR		__REG(0x40900028)  /* Stopwatch Count Register */
#define RTCPICR		__REG(0x40900034)  /* Periodic Interrupt Counter Register */

#define RTSR_PICE	(1 << 15)	/* Peridoc interrupt count enable */
#define RTSR_PIALE	(1 << 14)	/* Peridoc interrupt Alarm enable */
#define RTSR_PIAL	(1 << 13)	/* Peridoc  interrupt Alarm status */
#define RTSR_HZE	(1 << 3)	/* HZ interrupt enable */
#define RTSR_ALE	(1 << 2)	/* RTC alarm interrupt enable */
#define RTSR_HZ		(1 << 1)	/* HZ rising-edge detected */
#define RTSR_AL		(1 << 0)	/* RTC alarm detected */

/*
 * OS Timer & Match Registers
 */
#define OSMR0		__REG(0x40A00000)  /* OS Timer Match Register 0 */
#define OSMR1		__REG(0x40A00004)  /* OS Timer Match Register 1 */
#define OSMR2		__REG(0x40A00008)  /* OS Timer Match Register 2 */
#define OSMR3		__REG(0x40A0000C)  /* OS Timer Match Register 3 */
#define OSCR		__REG(0x40A00010)  /* OS Timer Counter Register */
#define OSSR		__REG(0x40A00014)  /* OS Timer Status Register */
#define OWER		__REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
#define OIER		__REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */

#ifdef CONFIG_CPU_MONAHANS
#define OSCR4		__REG(0x40A00040)  /* OS Timer Counter Register 4 */
#define OSCR5		__REG(0x40A00044)  /* OS Timer Counter Register 5 */
#define OSCR6		__REG(0x40A00048)  /* OS Timer Counter Register 6 */
#define OSCR7		__REG(0x40A0004C)  /* OS Timer Counter Register 7 */
#define OSCR8		__REG(0x40A00050)  /* OS Timer Counter Register 8 */
#define OSCR9		__REG(0x40A00054)  /* OS Timer Counter Register 9 */
#define OSCR10		__REG(0x40A00058)  /* OS Timer Counter Register 10 */
#define OSCR11		__REG(0x40A0005C)  /* OS Timer Counter Register 11 */

#define OSMR4		__REG(0x40A00080)  /* OS Timer Match Register 4 */
#define OSMR5		__REG(0x40A00084)  /* OS Timer Match Register 5 */
#define OSMR6		__REG(0x40A00088)  /* OS Timer Match Register 6 */
#define OSMR7		__REG(0x40A0008C)  /* OS Timer Match Register 7 */
#define OSMR8		__REG(0x40A00090)  /* OS Timer Match Register 8 */
#define OSMR9		__REG(0x40A00094)  /* OS Timer Match Register 9 */
#define OSMR10		__REG(0x40A00098)  /* OS Timer Match Register 10 */
#define OSMR11		__REG(0x40A0009C)  /* OS Timer Match Register 11 */

#define OMCR4		__REG(0x40A000C0)  /* OS Match Control Register 4 */
#define OMCR5		__REG(0x40A000C4)  /* OS Match Control Register 5 */
#define OMCR6		__REG(0x40A000C8)  /* OS Match Control Register 6 */
#define OMCR7		__REG(0x40A000CC)  /* OS Match Control Register 7 */
#define OMCR8		__REG(0x40A000D0)  /* OS Match Control Register 8 */
#define OMCR9		__REG(0x40A000D4)  /* OS Match Control Register 9 */
#define OMCR10		__REG(0x40A000D8)  /* OS Match Control Register 10 */
#define OMCR11		__REG(0x40A000DC)  /* OS Match Control Register 11 */

#define OSCR_CLK_FREQ	 3.250		   /* MHz */
#endif /* CONFIG_CPU_MONAHANS */

#define OSSR_M4		(1 << 4)	/* Match status channel 4 */
#define OSSR_M3		(1 << 3)	/* Match status channel 3 */
#define OSSR_M2		(1 << 2)	/* Match status channel 2 */
#define OSSR_M1		(1 << 1)	/* Match status channel 1 */
#define OSSR_M0		(1 << 0)	/* Match status channel 0 */

#define OWER_WME	(1 << 0)	/* Watchdog Match Enable */

#define OIER_E4		(1 << 4)	/* Interrupt enable channel 4 */
#define OIER_E3		(1 << 3)	/* Interrupt enable channel 3 */
#define OIER_E2		(1 << 2)	/* Interrupt enable channel 2 */
#define OIER_E1		(1 << 1)	/* Interrupt enable channel 1 */
#define OIER_E0		(1 << 0)	/* Interrupt enable channel 0 */

/*
 * Pulse Width Modulator
 */
#define PWM_CTRL0	__REG(0x40B00000)  /* PWM 0 Control Register */
#define PWM_PWDUTY0	__REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
#define PWM_PERVAL0	__REG(0x40B00008)  /* PWM 0 Period Control Register */

#define PWM_CTRL1	__REG(0x40C00000)  /* PWM 1Control Register */
#define PWM_PWDUTY1	__REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
#define PWM_PERVAL1	__REG(0x40C00008)  /* PWM 1 Period Control Register */

/*
 * Interrupt Controller
 */
#define ICIP		__REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
#define ICMR		__REG(0x40D00004)  /* Interrupt Controller Mask Register */
#define ICLR		__REG(0x40D00008)  /* Interrupt Controller Level Register */
#define ICFP		__REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
#define ICPR		__REG(0x40D00010)  /* Interrupt Controller Pending Register */
#define ICCR		__REG(0x40D00014)  /* Interrupt Controller Control Register */

#ifdef CONFIG_CPU_MONAHANS
#define ICHP		__REG(0x40D00018)  /* Interrupt Controller Highest Priority Register */
/* Missing: 32 Interrupt priority registers
 * These are the same as beneath for PXA27x: maybe can be merged if
 * GPIO Stuff is same too.
 */
#define ICIP2		__REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
#define ICMR2		__REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
#define ICLR2		__REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
#define ICFP2		__REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
#define ICPR2		__REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
/* Missing: 2 Interrupt priority registers */
#endif /* CONFIG_CPU_MONAHANS */

/*
 * General Purpose I/O
 */
#define GPLR0		__REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
#define GPLR1		__REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
#define GPLR2		__REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */

#define GPDR0		__REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
#define GPDR1		__REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
#define GPDR2		__REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */

#define GPSR0		__REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
#define GPSR1		__REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
#define GPSR2		__REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */

#define GPCR0		__REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
#define GPCR1		__REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
#define GPCR2		__REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */

#define GRER0		__REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
#define GRER1		__REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
#define GRER2		__REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */

#define GFER0		__REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
#define GFER1		__REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
#define GFER2		__REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */

#define GEDR0		__REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
#define GEDR1		__REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
#define GEDR2		__REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */

#ifdef CONFIG_CPU_MONAHANS
#define GPLR3		__REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
#define GPDR3		__REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
#define GPSR3		__REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
#define GPCR3		__REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
#define GRER3		__REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
#define GFER3		__REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
#define GEDR3		__REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */

#define GSDR0		__REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
#define GSDR1		__REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
#define GSDR2		__REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
#define GSDR3		__REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */

#define GCDR0		__REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
#define GCDR1		__REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
#define GCDR2		__REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
#define GCDR3		__REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */

#define GSRER0		__REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
#define GSRER1		__REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
#define GSRER2		__REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
#define GSRER3		__REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */

#define GCRER0		__REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
#define GCRER1		__REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
#define GCRER2		__REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
#define GCRER3		__REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */

#define GSFER0		__REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
#define GSFER1		__REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
#define GSFER2		__REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
#define GSFER3		__REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */

#define GCFER0		__REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
#define GCFER1		__REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
#define GCFER2		__REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
#define GCFER3		__REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */

#define GSDR(x)		__REG2(0x40E00400, ((x) & 0x60) >> 3)
#define GCDR(x)		__REG2(0x40300420, ((x) & 0x60) >> 3)

/* Multi-funktion Pin Registers, uncomplete, only:
 *    - GPIO
 *    - Data Flash DF_* pins defined.
 */
#define GPIO0		__REG(0x40e10124)
#define GPIO1		__REG(0x40e10128)
#define GPIO2		__REG(0x40e1012c)
#define GPIO3		__REG(0x40e10130)
#define GPIO4		__REG(0x40e10134)
#define nXCVREN		__REG(0x40e10138)

#define DF_CLE_NOE	__REG(0x40e10204)
#define DF_ALE_WE1	__REG(0x40e10208)

#define DF_SCLK_E	__REG(0x40e10210)
#define nBE0		__REG(0x40e10214)
#define nBE1		__REG(0x40e10218)
#define DF_ALE_WE2	__REG(0x40e1021c)
#define DF_INT_RnB	__REG(0x40e10220)
#define DF_nCS0		__REG(0x40e10224)
#define DF_nCS1		__REG(0x40e10228)
#define DF_nWE		__REG(0x40e1022c)
#define DF_nRE		__REG(0x40e10230)
#define nLUA		__REG(0x40e10234)
#define nLLA		__REG(0x40e10238)
#define DF_ADDR0	__REG(0x40e1023c)
#define DF_ADDR1	__REG(0x40e10240)
#define DF_ADDR2	__REG(0x40e10244)
#define DF_ADDR3	__REG(0x40e10248)
#define DF_IO0		__REG(0x40e1024c)
#define DF_IO8		__REG(0x40e10250)
#define DF_IO1		__REG(0x40e10254)
#define DF_IO9		__REG(0x40e10258)
#define DF_IO2		__REG(0x40e1025c)
#define DF_IO10		__REG(0x40e10260)
#define DF_IO3		__REG(0x40e10264)
#define DF_IO11		__REG(0x40e10268)
#define DF_IO4		__REG(0x40e1026c)
#define DF_IO12		__REG(0x40e10270)
#define DF_IO5		__REG(0x40e10274)
#define DF_IO13		__REG(0x40e10278)
#define DF_IO6		__REG(0x40e1027c)
#define DF_IO14		__REG(0x40e10280)
#define DF_IO7		__REG(0x40e10284)
#define DF_IO15		__REG(0x40e10288)

#define GPIO5		__REG(0x40e1028c)
#define GPIO6		__REG(0x40e10290)
#define GPIO7		__REG(0x40e10294)
#define GPIO8		__REG(0x40e10298)
#define GPIO9		__REG(0x40e1029c)

#define GPIO11		__REG(0x40e102a0)
#define GPIO12		__REG(0x40e102a4)
#define GPIO13		__REG(0x40e102a8)
#define GPIO14		__REG(0x40e102ac)
#define GPIO15		__REG(0x40e102b0)
#define GPIO16		__REG(0x40e102b4)
#define GPIO17		__REG(0x40e102b8)
#define GPIO18		__REG(0x40e102bc)
#define GPIO19		__REG(0x40e102c0)
#define GPIO20		__REG(0x40e102c4)
#define GPIO21		__REG(0x40e102c8)
#define GPIO22		__REG(0x40e102cc)
#define GPIO23		__REG(0x40e102d0)
#define GPIO24		__REG(0x40e102d4)
#define GPIO25		__REG(0x40e102d8)
#define GPIO26		__REG(0x40e102dc)