adc.tan.rpt

对AD0809进行操作

; N/A   ; None         ; 2.284 ns   ; rst_n   ; data_r[6]  ; clk      ;
; N/A   ; None         ; 2.284 ns   ; rst_n   ; data_r[7]  ; clk      ;
; N/A   ; None         ; 1.288 ns   ; data[3] ; data_r[3]  ; clk      ;
; N/A   ; None         ; 1.182 ns   ; data[0] ; data_r[0]  ; clk      ;
; N/A   ; None         ; 1.173 ns   ; data[2] ; data_r[2]  ; clk      ;
; N/A   ; None         ; 1.115 ns   ; data[4] ; data_r[4]  ; clk      ;
; N/A   ; None         ; 1.002 ns   ; data[5] ; data_r[5]  ; clk      ;
; N/A   ; None         ; 0.852 ns   ; data[1] ; data_r[1]  ; clk      ;
; N/A   ; None         ; 0.778 ns   ; data[6] ; data_r[6]  ; clk      ;
; N/A   ; None         ; 0.696 ns   ; eoc     ; oe~reg0    ; clk      ;
; N/A   ; None         ; 0.669 ns   ; data[7] ; data_r[7]  ; clk      ;
; N/A   ; None         ; 0.663 ns   ; eoc     ; ale~reg0   ; clk      ;
; N/A   ; None         ; 0.661 ns   ; eoc     ; state.st4  ; clk      ;
; N/A   ; None         ; 0.661 ns   ; eoc     ; start~reg0 ; clk      ;
; N/A   ; None         ; 0.392 ns   ; eoc     ; state.st5  ; clk      ;
+-------+--------------+------------+---------+------------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To     ; From Clock ;
+-------+--------------+------------+------------+--------+------------+
; N/A   ; None         ; 14.030 ns  ; start~reg0 ; start  ; clk        ;
; N/A   ; None         ; 14.017 ns  ; oe~reg0    ; oe     ; clk        ;
; N/A   ; None         ; 13.535 ns  ; ale~reg0   ; ale    ; clk        ;
; N/A   ; None         ; 13.229 ns  ; data_r[6]  ; out[6] ; clk        ;
; N/A   ; None         ; 13.161 ns  ; data_r[7]  ; out[7] ; clk        ;
; N/A   ; None         ; 13.048 ns  ; data_r[3]  ; out[3] ; clk        ;
; N/A   ; None         ; 13.040 ns  ; data_r[4]  ; out[4] ; clk        ;
; N/A   ; None         ; 13.028 ns  ; data_r[0]  ; out[0] ; clk        ;
; N/A   ; None         ; 13.025 ns  ; data_r[1]  ; out[1] ; clk        ;
; N/A   ; None         ; 13.004 ns  ; data_r[5]  ; out[5] ; clk        ;
; N/A   ; None         ; 12.994 ns  ; data_r[2]  ; out[2] ; clk        ;
; N/A   ; None         ; 10.156 ns  ; clk1_r     ; clk1   ; clk        ;
+-------+--------------+------------+------------+--------+------------+


+---------------------------------------------------------------------------+
; th                                                                        ;
+---------------+-------------+-----------+---------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To         ; To Clock ;
+---------------+-------------+-----------+---------+------------+----------+
; N/A           ; None        ; -0.126 ns ; eoc     ; state.st5  ; clk      ;
; N/A           ; None        ; -0.395 ns ; eoc     ; state.st4  ; clk      ;
; N/A           ; None        ; -0.395 ns ; eoc     ; start~reg0 ; clk      ;
; N/A           ; None        ; -0.397 ns ; eoc     ; ale~reg0   ; clk      ;
; N/A           ; None        ; -0.403 ns ; data[7] ; data_r[7]  ; clk      ;
; N/A           ; None        ; -0.430 ns ; eoc     ; oe~reg0    ; clk      ;
; N/A           ; None        ; -0.512 ns ; data[6] ; data_r[6]  ; clk      ;
; N/A           ; None        ; -0.586 ns ; data[1] ; data_r[1]  ; clk      ;
; N/A           ; None        ; -0.736 ns ; data[5] ; data_r[5]  ; clk      ;
; N/A           ; None        ; -0.849 ns ; data[4] ; data_r[4]  ; clk      ;
; N/A           ; None        ; -0.907 ns ; data[2] ; data_r[2]  ; clk      ;
; N/A           ; None        ; -0.916 ns ; data[0] ; data_r[0]  ; clk      ;
; N/A           ; None        ; -1.022 ns ; data[3] ; data_r[3]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[0]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[1]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[2]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[3]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[4]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[5]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[6]  ; clk      ;
; N/A           ; None        ; -2.018 ns ; rst_n   ; data_r[7]  ; clk      ;
+---------------+-------------+-----------+---------+------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sun May 24 14:44:56 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADC -c ADC --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk1_r" as buffer
Info: Clock "clk" has Internal fmax of 356.38 MHz between source register "state.st5" and destination register "data_r[0]" (period= 2.806 ns)
    Info: + Longest register to register delay is 2.538 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'
        Info: 2: + IC(0.430 ns) + CELL(0.206 ns) = 0.636 ns; Loc. = LCCOMB_X21_Y8_N4; Fanout = 8; COMB Node = 'data_r[0]~90'
        Info: 3: + IC(1.047 ns) + CELL(0.855 ns) = 2.538 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r[0]'
        Info: Total cell delay = 1.061 ns ( 41.80 % )
        Info: Total interconnect delay = 1.477 ns ( 58.20 % )
    Info: - Smallest clock skew is -0.004 ns
        Info: + Shortest clock path from clock "clk" to destination register is 7.362 ns
            Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'
            Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'
            Info: 4: + IC(0.840 ns) + CELL(0.666 ns) = 7.362 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r[0]'
            Info: Total cell delay = 2.631 ns ( 35.74 % )
            Info: Total interconnect delay = 4.731 ns ( 64.26 % )
        Info: - Longest clock path from clock "clk" to source register is 7.366 ns
            Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'
            Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'
            Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'
            Info: 4: + IC(0.844 ns) + CELL(0.666 ns) = 7.366 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'
            Info: Total cell delay = 2.631 ns ( 35.72 % )
            Info: Total interconnect delay = 4.735 ns ( 64.28 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tsu for register "data_r[0]" (data pin = "rst_n", clock pin = "clk") is 2.284 ns
    Info: + Longest pin to register delay is 9.686 ns
        Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_142; Fanout = 16; PIN Node = 'rst_n'
        Info: 2: + IC(6.210 ns) + CELL(0.589 ns) = 7.784 ns; Loc. = LCCOMB_X21_Y8_N4; Fanout = 8; COMB Node = 'data_r[0]~90'
        Info: 3: + IC(1.047 ns) + CELL(0.855 ns) = 9.686 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r[0]'
        Info: Total cell delay = 2.429 ns ( 25.08 % )
        Info: Total interconnect delay = 7.257 ns ( 74.92 % )
    Info: + Micro setup delay of destination is -0.040 ns
    Info: - Shortest clock path from clock "clk" to destination register is 7.362 ns
        Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'
        Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'
        Info: 4: + IC(0.840 ns) + CELL(0.666 ns) = 7.362 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r[0]'
        Info: Total cell delay = 2.631 ns ( 35.74 % )
        Info: Total interconnect delay = 4.731 ns ( 64.26 % )
Info: tco from clock "clk" to destination pin "start" through register "start~reg0" is 14.030 ns
    Info: + Longest clock path from clock "clk" to source register is 7.366 ns
        Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'
        Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'
        Info: 4: + IC(0.844 ns) + CELL(0.666 ns) = 7.366 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 2; REG Node = 'start~reg0'
        Info: Total cell delay = 2.631 ns ( 35.72 % )
        Info: Total interconnect delay = 4.735 ns ( 64.28 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 6.360 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 2; REG Node = 'start~reg0'
        Info: 2: + IC(3.264 ns) + CELL(3.096 ns) = 6.360 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'start'
        Info: Total cell delay = 3.096 ns ( 48.68 % )
        Info: Total interconnect delay = 3.264 ns ( 51.32 % )
Info: th for register "state.st5" (data pin = "eoc", clock pin = "clk") is -0.126 ns
    Info: + Longest clock path from clock "clk" to destination register is 7.366 ns
        Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'
        Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'
        Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'
        Info: 4: + IC(0.844 ns) + CELL(0.666 ns) = 7.366 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'
        Info: Total cell delay = 2.631 ns ( 35.72 % )
        Info: Total interconnect delay = 4.735 ns ( 64.28 % )
    Info: + Micro hold delay of destination is 0.306 ns
    Info: - Shortest pin to register delay is 7.798 ns
        Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 5; PIN Node = 'eoc'
        Info: 2: + IC(6.339 ns) + CELL(0.366 ns) = 7.690 ns; Loc. = LCCOMB_X21_Y8_N0; Fanout = 1; COMB Node = 'state~35'
        Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.798 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'
        Info: Total cell delay = 1.459 ns ( 18.71 % )
        Info: Total interconnect delay = 6.339 ns ( 81.29 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 124 megabytes
    Info: Processing ended: Sun May 24 14:44:57 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01