adc.tan.qmsg

对AD0809进行操作

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1_r " "Info: Detected ripple clock \"clk1_r\" as buffer" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state.st5 register data_r\[0\] 356.38 MHz 2.806 ns Internal " "Info: Clock \"clk\" has Internal fmax of 356.38 MHz between source register \"state.st5\" and destination register \"data_r\[0\]\" (period= 2.806 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.538 ns + Longest register register " "Info: + Longest register to register delay is 2.538 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.st5 1 REG LCFF_X21_Y8_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.st5 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.430 ns) + CELL(0.206 ns) 0.636 ns data_r\[0\]~90 2 COMB LCCOMB_X21_Y8_N4 8 " "Info: 2: + IC(0.430 ns) + CELL(0.206 ns) = 0.636 ns; Loc. = LCCOMB_X21_Y8_N4; Fanout = 8; COMB Node = 'data_r\[0\]~90'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.636 ns" { state.st5 data_r[0]~90 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.855 ns) 2.538 ns data_r\[0\] 3 REG LCFF_X22_Y5_N25 1 " "Info: 3: + IC(1.047 ns) + CELL(0.855 ns) = 2.538 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.902 ns" { data_r[0]~90 data_r[0] } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.061 ns ( 41.80 % ) " "Info: Total cell delay = 1.061 ns ( 41.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.477 ns ( 58.20 % ) " "Info: Total interconnect delay = 1.477 ns ( 58.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.538 ns" { state.st5 data_r[0]~90 data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.538 ns" { state.st5 {} data_r[0]~90 {} data_r[0] {} } { 0.000ns 0.430ns 1.047ns } { 0.000ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.362 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.362 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns clk 1 CLK PIN_15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(0.970 ns) 3.962 ns clk1_r 2 REG LCFF_X21_Y8_N21 3 " "Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.967 ns" { clk clk1_r } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.000 ns) 5.856 ns clk1_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { clk1_r clk1_r~clkctrl } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.666 ns) 7.362 ns data_r\[0\] 4 REG LCFF_X22_Y5_N25 1 " "Info: 4: + IC(0.840 ns) + CELL(0.666 ns) = 7.362 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.506 ns" { clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.631 ns ( 35.74 % ) " "Info: Total cell delay = 2.631 ns ( 35.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.731 ns ( 64.26 % ) " "Info: Total interconnect delay = 4.731 ns ( 64.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.362 ns" { clk clk1_r clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.362 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} data_r[0] {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.840ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.366 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns clk 1 CLK PIN_15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(0.970 ns) 3.962 ns clk1_r 2 REG LCFF_X21_Y8_N21 3 " "Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.967 ns" { clk clk1_r } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.000 ns) 5.856 ns clk1_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { clk1_r clk1_r~clkctrl } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.666 ns) 7.366 ns state.st5 4 REG LCFF_X21_Y8_N1 3 " "Info: 4: + IC(0.844 ns) + CELL(0.666 ns) = 7.366 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.631 ns ( 35.72 % ) " "Info: Total cell delay = 2.631 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.735 ns ( 64.28 % ) " "Info: Total interconnect delay = 4.735 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} state.st5 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.362 ns" { clk clk1_r clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.362 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} data_r[0] {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.840ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} state.st5 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.538 ns" { state.st5 data_r[0]~90 data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.538 ns" { state.st5 {} data_r[0]~90 {} data_r[0] {} } { 0.000ns 0.430ns 1.047ns } { 0.000ns 0.206ns 0.855ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.362 ns" { clk clk1_r clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.362 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} data_r[0] {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.840ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} state.st5 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "data_r\[0\] rst_n clk 2.284 ns register " "Info: tsu for register \"data_r\[0\]\" (data pin = \"rst_n\", clock pin = \"clk\") is 2.284 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.686 ns + Longest pin register " "Info: + Longest pin to register delay is 9.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns rst_n 1 PIN PIN_142 16 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_142; Fanout = 16; PIN Node = 'rst_n'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_n } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.210 ns) + CELL(0.589 ns) 7.784 ns data_r\[0\]~90 2 COMB LCCOMB_X21_Y8_N4 8 " "Info: 2: + IC(6.210 ns) + CELL(0.589 ns) = 7.784 ns; Loc. = LCCOMB_X21_Y8_N4; Fanout = 8; COMB Node = 'data_r\[0\]~90'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.799 ns" { rst_n data_r[0]~90 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.047 ns) + CELL(0.855 ns) 9.686 ns data_r\[0\] 3 REG LCFF_X22_Y5_N25 1 " "Info: 3: + IC(1.047 ns) + CELL(0.855 ns) = 9.686 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.902 ns" { data_r[0]~90 data_r[0] } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.429 ns ( 25.08 % ) " "Info: Total cell delay = 2.429 ns ( 25.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.257 ns ( 74.92 % ) " "Info: Total interconnect delay = 7.257 ns ( 74.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.686 ns" { rst_n data_r[0]~90 data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.686 ns" { rst_n {} rst_n~combout {} data_r[0]~90 {} data_r[0] {} } { 0.000ns 0.000ns 6.210ns 1.047ns } { 0.000ns 0.985ns 0.589ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.362 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.362 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns clk 1 CLK PIN_15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(0.970 ns) 3.962 ns clk1_r 2 REG LCFF_X21_Y8_N21 3 " "Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.967 ns" { clk clk1_r } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.000 ns) 5.856 ns clk1_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { clk1_r clk1_r~clkctrl } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.840 ns) + CELL(0.666 ns) 7.362 ns data_r\[0\] 4 REG LCFF_X22_Y5_N25 1 " "Info: 4: + IC(0.840 ns) + CELL(0.666 ns) = 7.362 ns; Loc. = LCFF_X22_Y5_N25; Fanout = 1; REG Node = 'data_r\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.506 ns" { clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.631 ns ( 35.74 % ) " "Info: Total cell delay = 2.631 ns ( 35.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.731 ns ( 64.26 % ) " "Info: Total interconnect delay = 4.731 ns ( 64.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.362 ns" { clk clk1_r clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.362 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} data_r[0] {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.840ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.686 ns" { rst_n data_r[0]~90 data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.686 ns" { rst_n {} rst_n~combout {} data_r[0]~90 {} data_r[0] {} } { 0.000ns 0.000ns 6.210ns 1.047ns } { 0.000ns 0.985ns 0.589ns 0.855ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.362 ns" { clk clk1_r clk1_r~clkctrl data_r[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.362 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} data_r[0] {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.840ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk start start~reg0 14.030 ns register " "Info: tco from clock \"clk\" to destination pin \"start\" through register \"start~reg0\" is 14.030 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.366 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns clk 1 CLK PIN_15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(0.970 ns) 3.962 ns clk1_r 2 REG LCFF_X21_Y8_N21 3 " "Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.967 ns" { clk clk1_r } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.000 ns) 5.856 ns clk1_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { clk1_r clk1_r~clkctrl } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.666 ns) 7.366 ns start~reg0 4 REG LCFF_X21_Y8_N23 2 " "Info: 4: + IC(0.844 ns) + CELL(0.666 ns) = 7.366 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 2; REG Node = 'start~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { clk1_r~clkctrl start~reg0 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.631 ns ( 35.72 % ) " "Info: Total cell delay = 2.631 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.735 ns ( 64.28 % ) " "Info: Total interconnect delay = 4.735 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl start~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} start~reg0 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.360 ns + Longest register pin " "Info: + Longest register to pin delay is 6.360 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns start~reg0 1 REG LCFF_X21_Y8_N23 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y8_N23; Fanout = 2; REG Node = 'start~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { start~reg0 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.264 ns) + CELL(3.096 ns) 6.360 ns start 2 PIN PIN_31 0 " "Info: 2: + IC(3.264 ns) + CELL(3.096 ns) = 6.360 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'start'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.360 ns" { start~reg0 start } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 48.68 % ) " "Info: Total cell delay = 3.096 ns ( 48.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.264 ns ( 51.32 % ) " "Info: Total interconnect delay = 3.264 ns ( 51.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.360 ns" { start~reg0 start } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.360 ns" { start~reg0 {} start {} } { 0.000ns 3.264ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl start~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} start~reg0 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.360 ns" { start~reg0 start } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.360 ns" { start~reg0 {} start {} } { 0.000ns 3.264ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}