prev_cmp_adc.tan.qmsg

对AD0809进行操作

{ "Info" "ITDB_TH_RESULT" "state.st5 eoc clk -0.126 ns register " "Info: th for register \"state.st5\" (data pin = \"eoc\", clock pin = \"clk\") is -0.126 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.366 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.366 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns clk 1 CLK PIN_15 6 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_15; Fanout = 6; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.997 ns) + CELL(0.970 ns) 3.962 ns clk1_r 2 REG LCFF_X21_Y8_N21 3 " "Info: 2: + IC(1.997 ns) + CELL(0.970 ns) = 3.962 ns; Loc. = LCFF_X21_Y8_N21; Fanout = 3; REG Node = 'clk1_r'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.967 ns" { clk clk1_r } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.894 ns) + CELL(0.000 ns) 5.856 ns clk1_r~clkctrl 3 COMB CLKCTRL_G5 17 " "Info: 3: + IC(1.894 ns) + CELL(0.000 ns) = 5.856 ns; Loc. = CLKCTRL_G5; Fanout = 17; COMB Node = 'clk1_r~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.894 ns" { clk1_r clk1_r~clkctrl } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.844 ns) + CELL(0.666 ns) 7.366 ns state.st5 4 REG LCFF_X21_Y8_N1 3 " "Info: 4: + IC(0.844 ns) + CELL(0.666 ns) = 7.366 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.510 ns" { clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.631 ns ( 35.72 % ) " "Info: Total cell delay = 2.631 ns ( 35.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.735 ns ( 64.28 % ) " "Info: Total interconnect delay = 4.735 ns ( 64.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} state.st5 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.798 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns eoc 1 PIN PIN_32 5 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_32; Fanout = 5; PIN Node = 'eoc'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { eoc } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.339 ns) + CELL(0.366 ns) 7.690 ns state~35 2 COMB LCCOMB_X21_Y8_N0 1 " "Info: 2: + IC(6.339 ns) + CELL(0.366 ns) = 7.690 ns; Loc. = LCCOMB_X21_Y8_N0; Fanout = 1; COMB Node = 'state~35'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.705 ns" { eoc state~35 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.798 ns state.st5 3 REG LCFF_X21_Y8_N1 3 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.798 ns; Loc. = LCFF_X21_Y8_N1; Fanout = 3; REG Node = 'state.st5'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { state~35 state.st5 } "NODE_NAME" } } { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.459 ns ( 18.71 % ) " "Info: Total cell delay = 1.459 ns ( 18.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.339 ns ( 81.29 % ) " "Info: Total interconnect delay = 6.339 ns ( 81.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.798 ns" { eoc state~35 state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.798 ns" { eoc {} eoc~combout {} state~35 {} state.st5 {} } { 0.000ns 0.000ns 6.339ns 0.000ns } { 0.000ns 0.985ns 0.366ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.366 ns" { clk clk1_r clk1_r~clkctrl state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.366 ns" { clk {} clk~combout {} clk1_r {} clk1_r~clkctrl {} state.st5 {} } { 0.000ns 0.000ns 1.997ns 1.894ns 0.844ns } { 0.000ns 0.995ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.798 ns" { eoc state~35 state.st5 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.798 ns" { eoc {} eoc~combout {} state~35 {} state.st5 {} } { 0.000ns 0.000ns 6.339ns 0.000ns } { 0.000ns 0.985ns 0.366ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "123 " "Info: Peak virtual memory: 123 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri May 22 15:17:49 2009 " "Info: Processing ended: Fri May 22 15:17:49 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}