adc.fit.rpt

对AD0809进行操作

; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 61      ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 25 / 4,608 ( < 1 % ) ;
;     -- Combinational with no register       ; 2                    ;
;     -- Register only                        ; 10                   ;
;     -- Combinational with a register        ; 13                   ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 4                    ;
;     -- 3 input functions                    ; 3                    ;
;     -- <=2 input functions                  ; 8                    ;
;     -- Register only                        ; 10                   ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 12                   ;
;     -- arithmetic mode                      ; 3                    ;
;                                             ;                      ;
; Total registers*                            ; 23 / 5,010 ( < 1 % ) ;
;     -- Dedicated logic registers            ; 23 / 4,608 ( < 1 % ) ;
;     -- I/O registers                        ; 0 / 402 ( 0 % )      ;
;                                             ;                      ;
; Total LABs:  partially or completely used   ; 3 / 288 ( 1 % )      ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 23 / 142 ( 16 % )    ;
;     -- Clock pins                           ; 0 / 4 ( 0 % )        ;
; Global signals                              ; 1                    ;
; M4Ks                                        ; 0 / 26 ( 0 % )       ;
; Total memory bits                           ; 0 / 119,808 ( 0 % )  ;
; Total RAM block bits                        ; 0 / 119,808 ( 0 % )  ;
; Embedded Multiplier 9-bit elements          ; 0 / 26 ( 0 % )       ;
; PLLs                                        ; 0 / 2 ( 0 % )        ;
; Global clocks                               ; 1 / 8 ( 13 % )       ;
; JTAGs                                       ; 0 / 1 ( 0 % )        ;
; Average interconnect usage (total/H/V)      ; 0% / 0% / 0%         ;
; Peak interconnect usage (total/H/V)         ; 0% / 0% / 0%         ;
; Maximum fan-out node                        ; clk1_r~clkctrl       ;
; Maximum fan-out                             ; 17                   ;
; Highest non-global fan-out signal           ; rst_n                ;
; Highest non-global fan-out                  ; 16                   ;
; Total fan-out                               ; 124                  ;
; Average fan-out                             ; 1.77                 ;
+---------------------------------------------+----------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                    ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk     ; 15    ; 1        ; 0            ; 11           ; 3           ; 6                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; data[0] ; 3     ; 1        ; 0            ; 13           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;
; data[1] ; 4     ; 1        ; 0            ; 13           ; 3           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; User                 ;