📄 ebiu.c
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#include <cdefBF533.h>
#include <ccblkfn.h>
//Setup of the async interface
void Init_EBIU()
{
if (*pEBIU_SDSTAT & SDRS)
{
//SDRAM Refresh Rate Control Register
*pEBIU_SDRRC = 0x00000817;
//SDRAM Memory Bank Control Register
*pEBIU_SDBCTL = 0x00000013;
//SDRAM Memory Global Control Register
*pEBIU_SDGCTL = 0x0091998d;
ssync();
}
*pEBIU_AMBCTL0 = 0x7bb07bb0; // <--|Write access time = 7 cycles, read access time = 11 cycles, no ARDY
//ams3->ads8364
//setup 0ns, read 60ns, hold 10ns
//1 cycle, 9 cycles, 2 cycles
//write read hold setup transition
//0111 1001 10 01 00 0 0
//ams2->KM29U128T(dataflash)
//(Trc/Twc)r/w cycle time 50ns (setup+rw+hold)
// /awe, (Twp)low min 25ns(write); (Twh)high min 15ns(hold+setup)
//setup 0ns, write min 25ns, hold 10ns
//1 cycle, 4 cycles, 2 cycles
//setup 0ns, read 35ns, hold 15ns
//1 cycle, 5 cycles, 2 cycles
//write read hold setup transition
//0100 0101 10 01 00 0 0
//status cmd, cmd write between status return min 60ns, use delay to achieve
// *pEBIU_AMBCTL1 = 0x79904590;
*pEBIU_AMBCTL1 = 0x7990FFC3;
*pEBIU_AMGCTL |= 0x000F;
}//end Init_EBIU
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