📄 ps2_mouse9.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY ps2_mouse9 IS -- 顶层设计
PORT ( CLK1 : IN STD_LOGIC;
CODE1 : OUT std_logic_vector(3 downto 0);
SPKS : OUT STD_LOGIC ;
reset : in std_logic;
clk : in std_logic; -- 750kHz
ps2_clk : INOUT STD_LOGIC;
ps2_data : INOUT STD_LOGIC;
-------------------------------------------------
ps2_clk00 : INOUT STD_LOGIC;
ps2_data00 : INOUT STD_LOGIC;
-------------------------------------------
enk_1 : out std_logic;
---------------------------------------
ps2_data2 : out std_logic_vector(7 downto 0);
---------------------------------------------------------
ps2_data2A : out std_logic_vector(7 downto 0);
ps2_data3A : out std_logic_vector(7 downto 0)
);
END ps2_mouse9;
ARCHITECTURE bdf_type OF ps2_mouse9 IS
---------------------------------------------------------------
COMPONENT PS2
port
( reset0 : in std_logic;
clk0 : in std_logic; -- 750kHz
ps2_clk0 : INOUT STD_LOGIC;
ps2_data0 : INOUT STD_LOGIC;
-------------------------------------------
ps2_data20 : out std_logic_vector(7 downto 0);
ps2_data30 : out std_logic_vector(7 downto 0)
);
END COMPONENT;
SIGNAL DATA0 : std_logic_vector(7 downto 0);
---------------------------------------------------------------
SIGNAL PreCLK , FullSpkS : STD_LOGIC;
signal TONE : INTEGER RANGE 0 TO 16#7FF#;
signal senddata : STD_LOGIC_VECTOR(11 DOWNTO 0);
constant ps2_f4 : std_logic_vector(10 downto 0) := B"10_11110100_0";
signal ps2_data_s : std_logic;
signal ps2_clk_s : std_logic;
signal enk : std_logic;
signal lowtimecount : std_logic_vector(6 downto 0);
signal ps2_clk_r : std_logic;
-----------------------------------------------------
signal flag : std_logic;
-----------------------------------------------------
signal always_one : std_logic;
signal q_data1_x : std_logic_vector(8 downto 0);
signal q_data2_x : std_logic_vector(8 downto 0);
signal q_data3_x : std_logic_vector(8 downto 0);
signal q_data4_x : std_logic_vector(8 downto 0);
signal q_data1 : std_logic_vector(7 downto 0);
signal q_data2 : std_logic_vector(7 downto 0);
signal q_data3 : std_logic_vector(7 downto 0);
signal q_data4 : std_logic_vector(7 downto 0);
signal count : std_logic_vector(3 downto 0);
----------------------------------------------
type statetype is ( m2_st0,m2_new,m2_st1,m2_st2,m2_st3,m2_st4,m2_st5,m2_st6,m2_st7,m2_st8,m2_st9,
m2_st10,m2_st11,m2_st12,m2_st13,m2_st14,m2_st15,m2_st16,m2_st17,m2_st18,m2_st19,
m2_st20,m2_st21,m2_st22,m2_st23,m2_st24,m2_st25,m2_st26,m2_st27,m2_st28,m2_st29,
m2_st30,m2_st31,m2_st32,m2_st33,m2_st34,m2_st35,m2_st36,m2_st37,m2_st38,m2_st39,
m2_st40,m2_st41,m2_st42,m2_st43,m2_st44,m2_st45,m2_st46);
signal m2_state,m2_nexts : statetype;
SIGNAL Tone2 : INTEGER RANGE 0 TO 16#7FF#;
SIGNAL INDEXV : STD_LOGIC_VECTOR(3 DOWNTO 0);
-----------------------------------
BEGIN
ps2_data_s <= senddata(0);
ps2_clk <= '0' when ps2_clk_s = '0' else 'Z';
ps2_data <= '0' when ps2_data_s = '0' else 'Z';
enk_1<= not enk;
--------------------------------------------------------
process(reset) begin
if reset'event and reset='0' then flag<='1';
end if;
end process;
----------------------------------------------------------
u1: process(clk,reset) begin
if reset = '1' then
lowtimecount <= (others => '0');
enk <= '0';
ps2_clk_s <= '1';
elsif falling_edge(clk) then
----------------------
if flag='1' then
---------------------
if lowtimecount < 100 then
lowtimecount <= lowtimecount + 1;
ps2_clk_s <= '0';
elsif lowtimecount <120 then
lowtimecount <= lowtimecount + 1;
enk <= '1';
else
ps2_clk_s <= '1';
enk <= '0';
end if;
end if;
end if;
end process;
u2:process(clk) begin
if falling_edge(clk) then
ps2_clk_r <= ps2_clk;
end if;
end process;
u3:process(ps2_clk_r,enk) begin
if enk = '1' then
senddata <= '1' & ps2_f4 ;
elsif falling_edge(ps2_clk_r) then
senddata(11 downto 0) <= '1' & senddata(11 downto 1);
end if;
end process;
------------------------------------------------Receve part--------------------------
con: process( enk,ps2_clk_r)
begin
if enk='1' then
count<=(others=>'0'); --count
elsif(ps2_clk_r'event and ps2_clk_r='0') then --receive at rising_edfe
if count<15 then
count<=count+1;
end if;
end if;
end process;
u4: process(clk)
begin
if(clk'event and clk='1') then
m2_state<=m2_nexts;
end if;
end process;
u5: process(ps2_clk_r,count,ps2_data)
begin
if(count<10) then
m2_nexts<=m2_st0;
elsif(ps2_clk_r'event and ps2_clk_r='1') then
case m2_state is
when m2_st0=> --------------------
-- m2_nexts<=m2_new;
m2_nexts<=m2_st1;
when m2_st1=> m2_nexts<=m2_st3;
------------------------------
when m2_st3=> m2_nexts<=m2_st4; --start
when m2_st4=> m2_nexts<=m2_st5; --data0
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st5=> m2_nexts<=m2_st6;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st6=> m2_nexts<=m2_st7;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st7=> m2_nexts<=m2_st8;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st8=> m2_nexts<=m2_st9;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st9=> m2_nexts<=m2_st10;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st10=> m2_nexts<=m2_st11;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
when m2_st11=> m2_nexts<=m2_st12;
q_data1_x<=ps2_data&q_data1_x(8 downto 1); --data7
-- q_data1<=q_data1_x(8 downto 1);
when m2_st12=> m2_nexts<=m2_st13;
q_data1_x<=ps2_data&q_data1_x(8 downto 1);
q_data1<=q_data1_x(8 downto 1);
when m2_st13=> m2_nexts<=m2_st14;
---------------------------------------------------------------------
when m2_st14=> m2_nexts<=m2_st15;
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