ps2_mouse9.map.eqn

PS2键盘鼠标接口控制实现电子琴功能

--H1_q_a[3] is altsyncram:reduce_or_rtl_4|altsyncram_l9k:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[3]_PORT_A_address = BUS(q_data2_x[8], q_data2_x[7], q_data2_x[6], q_data2_x[5], q_data2_x[4], q_data2_x[3], q_data2_x[2], q_data2_x[1]);
H1_q_a[3]_PORT_A_address_reg = DFFE(H1_q_a[3]_PORT_A_address, H1_q_a[3]_clock_0, , , H1_q_a[3]_clock_enable_0);
H1_q_a[3]_clock_0 = ps2_clk_r;
H1_q_a[3]_clock_enable_0 = A1L602;
H1_q_a[3]_PORT_A_data_out = MEMORY(, , H1_q_a[3]_PORT_A_address_reg, , , , , , H1_q_a[3]_clock_0, , H1_q_a[3]_clock_enable_0, , , );
H1_q_a[3] = H1_q_a[3]_PORT_A_data_out[0];


--q_data2[2] is q_data2[2]
--operation mode is normal

q_data2[2]_lut_out = q_data2_x[3];
q_data2[2] = DFFEA(q_data2[2]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--q_data2[7] is q_data2[7]
--operation mode is normal

q_data2[7]_lut_out = q_data2_x[8];
q_data2[7] = DFFEA(q_data2[7]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--A1L912 is reduce_nor~176
--operation mode is normal

A1L912 = q_data2[2] & !q_data2[7];


--q_data2[6] is q_data2[6]
--operation mode is normal

q_data2[6]_lut_out = q_data2_x[7];
q_data2[6] = DFFEA(q_data2[6]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--q_data2[5] is q_data2[5]
--operation mode is normal

q_data2[5]_lut_out = q_data2_x[6];
q_data2[5] = DFFEA(q_data2[5]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--A1L022 is reduce_nor~177
--operation mode is normal

A1L022 = q_data2[6] & !q_data2[5];


--q_data2[4] is q_data2[4]
--operation mode is normal

q_data2[4]_lut_out = q_data2_x[5];
q_data2[4] = DFFEA(q_data2[4]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--q_data2[3] is q_data2[3]
--operation mode is normal

q_data2[3]_lut_out = q_data2_x[4];
q_data2[3] = DFFEA(q_data2[3]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--A1L122 is reduce_nor~178
--operation mode is normal

A1L122 = A1L912 & A1L022 & !q_data2[4] & !q_data2[3];


--q_data2[1] is q_data2[1]
--operation mode is normal

q_data2[1]_lut_out = q_data2_x[2];
q_data2[1] = DFFEA(q_data2[1]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--q_data2[0] is q_data2[0]
--operation mode is normal

q_data2[0]_lut_out = q_data2_x[1];
q_data2[0] = DFFEA(q_data2[0]_lut_out, ps2_clk_r, VCC, , A1L602, , );


--A1L222 is reduce_nor~179
--operation mode is normal

A1L222 = q_data2[1] & !q_data2[0];


--D1_q_data2[2] is ps2:uA|q_data2[2]
--operation mode is normal

D1_q_data2[2]_lut_out = D1_q_data2_x[3];
D1_q_data2[2] = DFFEA(D1_q_data2[2]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L621 is ps2:uA|ps2_data20[2]~9
--operation mode is normal

D1L621 = D1_q_data2[2] & !reset;


--D1_q_data2[1] is ps2:uA|q_data2[1]
--operation mode is normal

D1_q_data2[1]_lut_out = D1_q_data2_x[2];
D1_q_data2[1] = DFFEA(D1_q_data2[1]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L521 is ps2:uA|ps2_data20[1]~10
--operation mode is normal

D1L521 = D1_q_data2[1] & !reset;


--D1_q_data2[3] is ps2:uA|q_data2[3]
--operation mode is normal

D1_q_data2[3]_lut_out = D1_q_data2_x[4];
D1_q_data2[3] = DFFEA(D1_q_data2[3]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L721 is ps2:uA|ps2_data20[3]~8
--operation mode is normal

D1L721 = D1_q_data2[3] & !reset;


--D1_q_data2[0] is ps2:uA|q_data2[0]
--operation mode is normal

D1_q_data2[0]_lut_out = D1_q_data2_x[1];
D1_q_data2[0] = DFFEA(D1_q_data2[0]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L421 is ps2:uA|ps2_data20[0]~11
--operation mode is normal

D1L421 = D1_q_data2[0] & !reset;


--A1L712 is reduce_nor~0
--operation mode is normal

A1L712 = D1L621 # D1L521 # !D1L421 # !D1L721;


--A1L82 is INDEXV[0]~7
--operation mode is normal

A1L82 = H1_q_a[3] # A1L122 & A1L222 & A1L712;


--H1_q_a[1] is altsyncram:reduce_or_rtl_4|altsyncram_l9k:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[1]_PORT_A_address = BUS(q_data2_x[8], q_data2_x[7], q_data2_x[6], q_data2_x[5], q_data2_x[4], q_data2_x[3], q_data2_x[2], q_data2_x[1]);
H1_q_a[1]_PORT_A_address_reg = DFFE(H1_q_a[1]_PORT_A_address, H1_q_a[1]_clock_0, , , H1_q_a[1]_clock_enable_0);
H1_q_a[1]_clock_0 = ps2_clk_r;
H1_q_a[1]_clock_enable_0 = A1L602;
H1_q_a[1]_PORT_A_data_out = MEMORY(, , H1_q_a[1]_PORT_A_address_reg, , , , , , H1_q_a[1]_clock_0, , H1_q_a[1]_clock_enable_0, , , );
H1_q_a[1] = H1_q_a[1]_PORT_A_data_out[0];


--H1_q_a[2] is altsyncram:reduce_or_rtl_4|altsyncram_l9k:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[2]_PORT_A_address = BUS(q_data2_x[8], q_data2_x[7], q_data2_x[6], q_data2_x[5], q_data2_x[4], q_data2_x[3], q_data2_x[2], q_data2_x[1]);
H1_q_a[2]_PORT_A_address_reg = DFFE(H1_q_a[2]_PORT_A_address, H1_q_a[2]_clock_0, , , H1_q_a[2]_clock_enable_0);
H1_q_a[2]_clock_0 = ps2_clk_r;
H1_q_a[2]_clock_enable_0 = A1L602;
H1_q_a[2]_PORT_A_data_out = MEMORY(, , H1_q_a[2]_PORT_A_address_reg, , , , , , H1_q_a[2]_clock_0, , H1_q_a[2]_clock_enable_0, , , );
H1_q_a[2] = H1_q_a[2]_PORT_A_data_out[0];


--A1L322 is reduce_nor~180
--operation mode is normal

A1L322 = !q_data2[4] & !q_data2[3];


--A1L812 is reduce_nor~11
--operation mode is normal

A1L812 = A1L912 & A1L022 & A1L322 & A1L222;


--A1L92 is INDEXV[2]~157
--operation mode is normal

A1L92 = D1L621 # D1L421 # !D1L521 # !D1L721;


--A1L03 is INDEXV[2]~158
--operation mode is normal

A1L03 = H1_q_a[2] # A1L812 & A1L712 & A1L92;


--H1_q_a[0] is altsyncram:reduce_or_rtl_4|altsyncram_l9k:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 4
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[0]_PORT_A_address = BUS(q_data2_x[8], q_data2_x[7], q_data2_x[6], q_data2_x[5], q_data2_x[4], q_data2_x[3], q_data2_x[2], q_data2_x[1]);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , H1_q_a[0]_clock_enable_0);
H1_q_a[0]_clock_0 = ps2_clk_r;
H1_q_a[0]_clock_enable_0 = A1L602;
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , H1_q_a[0]_clock_enable_0, , , );
H1_q_a[0] = H1_q_a[0]_PORT_A_data_out[0];


--A1L422 is reduce_nor~181
--operation mode is normal

A1L422 = q_data2[5] & q_data2[4] & q_data2[3] & !q_data2[6];


--A1L23 is INDEXV[3]~159
--operation mode is normal

A1L23 = H1_q_a[0] # A1L912 & A1L222 & A1L422;


--INDEXV[3] is INDEXV[3]
--operation mode is normal

INDEXV[3] = A1L23 # A1L122 & (q_data2[1] $ q_data2[0]);


--A1L931 is Mux~6
--operation mode is normal

A1L931 = INDEXV[3] & (H1_q_a[1] & !A1L82 # !H1_q_a[1] & !A1L03);


--A1L831 is Mux~5
--operation mode is normal

A1L831 = A1L03 & !INDEXV[3];


--A1L041 is Mux~8
--operation mode is normal

A1L041 = H1_q_a[1] # INDEXV[3] & (A1L82 # A1L03);


--A1L141 is Mux~10
--operation mode is normal

A1L141 = A1L82 & (!H1_q_a[1] & !A1L03 # !INDEXV[3]);


--Count2 is Count2
--operation mode is normal

Count2_lut_out = !Count2;
Count2 = DFFEA(Count2_lut_out, FullSpkS, VCC, , , , );


--enk is enk
--operation mode is normal

enk_lut_out = A1L43;
enk = DFFEA(enk_lut_out, !clk, !reset, , A1L63, , );


--A1L071 is ps2_data2~8
--operation mode is normal

A1L071 = q_data2[7] & !reset;


--A1L171 is ps2_data2~9
--operation mode is normal

A1L171 = q_data2[6] & !reset;


--A1L271 is ps2_data2~10
--operation mode is normal

A1L271 = q_data2[5] & !reset;


--A1L371 is ps2_data2~11
--operation mode is normal

A1L371 = q_data2[4] & !reset;


--A1L471 is ps2_data2~12
--operation mode is normal

A1L471 = q_data2[3] & !reset;


--A1L571 is ps2_data2~13
--operation mode is normal

A1L571 = q_data2[2] & !reset;


--A1L671 is ps2_data2~14
--operation mode is normal

A1L671 = q_data2[1] & !reset;


--A1L771 is ps2_data2~15
--operation mode is normal

A1L771 = q_data2[0] & !reset;


--D1_q_data2[7] is ps2:uA|q_data2[7]
--operation mode is normal

D1_q_data2[7]_lut_out = D1_q_data2_x[8];
D1_q_data2[7] = DFFEA(D1_q_data2[7]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L131 is ps2:uA|ps2_data20[7]~12
--operation mode is normal

D1L131 = D1_q_data2[7] & !reset;


--D1_q_data2[6] is ps2:uA|q_data2[6]
--operation mode is normal

D1_q_data2[6]_lut_out = D1_q_data2_x[7];
D1_q_data2[6] = DFFEA(D1_q_data2[6]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L031 is ps2:uA|ps2_data20[6]~13
--operation mode is normal

D1L031 = D1_q_data2[6] & !reset;


--D1_q_data2[5] is ps2:uA|q_data2[5]
--operation mode is normal

D1_q_data2[5]_lut_out = D1_q_data2_x[6];
D1_q_data2[5] = DFFEA(D1_q_data2[5]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L921 is ps2:uA|ps2_data20[5]~14
--operation mode is normal

D1L921 = D1_q_data2[5] & !reset;


--D1_q_data2[4] is ps2:uA|q_data2[4]
--operation mode is normal

D1_q_data2[4]_lut_out = D1_q_data2_x[5];
D1_q_data2[4] = DFFEA(D1_q_data2[4]_lut_out, D1_ps2_clk_r, VCC, , D1L851, , );


--D1L821 is ps2:uA|ps2_data20[4]~15
--operation mode is normal

D1L821 = D1_q_data2[4] & !reset;


--D1_q_data3[7] is ps2:uA|q_data3[7]
--operation mode is normal

D1_q_data3[7]_lut_out = D1_q_data3_x[8];
D1_q_data3[7] = DFFEA(D1_q_data3[7]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L931 is ps2:uA|ps2_data30[7]~8
--operation mode is normal

D1L931 = D1_q_data3[7] & !reset;


--D1_q_data3[6] is ps2:uA|q_data3[6]
--operation mode is normal

D1_q_data3[6]_lut_out = D1_q_data3_x[7];
D1_q_data3[6] = DFFEA(D1_q_data3[6]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L831 is ps2:uA|ps2_data30[6]~9
--operation mode is normal

D1L831 = D1_q_data3[6] & !reset;


--D1_q_data3[5] is ps2:uA|q_data3[5]
--operation mode is normal

D1_q_data3[5]_lut_out = D1_q_data3_x[6];
D1_q_data3[5] = DFFEA(D1_q_data3[5]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L731 is ps2:uA|ps2_data30[5]~10
--operation mode is normal

D1L731 = D1_q_data3[5] & !reset;


--D1_q_data3[4] is ps2:uA|q_data3[4]
--operation mode is normal

D1_q_data3[4]_lut_out = D1_q_data3_x[5];
D1_q_data3[4] = DFFEA(D1_q_data3[4]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L631 is ps2:uA|ps2_data30[4]~11
--operation mode is normal

D1L631 = D1_q_data3[4] & !reset;


--D1_q_data3[3] is ps2:uA|q_data3[3]
--operation mode is normal

D1_q_data3[3]_lut_out = D1_q_data3_x[4];
D1_q_data3[3] = DFFEA(D1_q_data3[3]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L531 is ps2:uA|ps2_data30[3]~12
--operation mode is normal

D1L531 = D1_q_data3[3] & !reset;


--D1_q_data3[2] is ps2:uA|q_data3[2]
--operation mode is normal

D1_q_data3[2]_lut_out = D1_q_data3_x[3];
D1_q_data3[2] = DFFEA(D1_q_data3[2]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L431 is ps2:uA|ps2_data30[2]~13
--operation mode is normal

D1L431 = D1_q_data3[2] & !reset;


--D1_q_data3[1] is ps2:uA|q_data3[1]
--operation mode is normal

D1_q_data3[1]_lut_out = D1_q_data3_x[2];
D1_q_data3[1] = DFFEA(D1_q_data3[1]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L331 is ps2:uA|ps2_data30[1]~14
--operation mode is normal

D1L331 = D1_q_data3[1] & !reset;


--D1_q_data3[0] is ps2:uA|q_data3[0]
--operation mode is normal

D1_q_data3[0]_lut_out = D1_q_data3_x[1];
D1_q_data3[0] = DFFEA(D1_q_data3[0]_lut_out, D1_ps2_clk_r, VCC, , D1L871, , );


--D1L231 is ps2:uA|ps2_data30[0]~15
--operation mode is normal

D1L231 = D1_q_data3[0] & !reset;


--ps2_clk_r is ps2_clk_r
--operation mode is normal

ps2_clk_r_lut_out = A1L841;
ps2_clk_r = DFFEA(ps2_clk_r_lut_out, !clk, VCC, , , , );


--G1_safe_q[3] is lpm_counter:count_rtl_0|cntr_qu7:auto_generated|safe_q[3]
--operation mode is normal

G1_safe_q[3]_carry_eqn = G1L6;
G1_safe_q[3]_lut_out = G1_safe_q[3] $ G1_safe_q[3]_carry_eqn;
G1_safe_q[3] = DFFEA(G1_safe_q[3]_lut_out, !ps2_clk_r, !enk, , A1L73, , );


--A1L411Q is m2_state~34
--operation mode is normal

A1L411Q_lut_out = A1L86Q;
A1L411Q = DFFEA(A1L411Q_lut_out, clk, VCC, , , , );


--G1_safe_q[1] is lpm_counter:count_rtl_0|cntr_qu7:auto_generated|safe_q[1]
--operation mode is arithmetic

G1_safe_q[1]_carry_eqn = G1L2;
G1_safe_q[1]_lut_out = G1_safe_q[1] $ G1_safe_q[1]_carry_eqn;
G1_safe_q[1] = DFFEA(G1_safe_q[1]_lut_out, !ps2_clk_r, !enk, , A1L73, , );

--G1L4 is lpm_counter:count_rtl_0|cntr_qu7:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

G1L4 = CARRY(!G1L2 # !G1_safe_q[1]);


--G1_safe_q[2] is lpm_counter:count_rtl_0|cntr_qu7:auto_generated|safe_q[2]
--operation mode is arithmetic

G1_safe_q[2]_carry_eqn = G1L4;
G1_safe_q[2]_lut_out = G1_safe_q[2] $ !G1_safe_q[2]_carry_eqn;
G1_safe_q[2] = DFFEA(G1_safe_q[2]_lut_out, !ps2_clk_r, !enk, , A1L73, , );

--G1L6 is lpm_counter:count_rtl_0|cntr_qu7:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

G1L6 = CARRY(G1_safe_q[2] & !G1L4);


--A1L602 is q_data2[7]~0
--operation mode is normal

A1L602 = G1_safe_q[3] & A1L411Q & (G1_safe_q[1] # G1_safe_q[2]);


--q_data2_x[8] is q_data2_x[8]
--operation mode is normal

q_data2_x[8]_lut_out = A1L781;
q_data2_x[8] = DFFEA(q_data2_x[8]_lut_out, ps2_clk_r, VCC, , A1L612, , );


--q_data2_x[7] is q_data2_x[7]
--operation mode is normal