ps2_mouse9.tan.qmsg

PS2键盘鼠标接口控制实现电子琴功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK1 register \\GenSpkS:Count11\[4\] register \\GenSpkS:Count11\[8\] 174.58 MHz 5.728 ns Internal " "Info: Clock \"CLK1\" has Internal fmax of 174.58 MHz between source register \"\\GenSpkS:Count11\[4\]\" and destination register \"\\GenSpkS:Count11\[8\]\" (period= 5.728 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.508 ns + Longest register register " "Info: + Longest register to register delay is 4.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\GenSpkS:Count11\[4\] 1 REG LC_X26_Y9_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N9; Fanout = 3; REG Node = '\\GenSpkS:Count11\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { \GenSpkS:Count11[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.590 ns) 1.146 ns Equal2~99 2 COMB LC_X26_Y9_N3 2 " "Info: 2: + IC(0.556 ns) + CELL(0.590 ns) = 1.146 ns; Loc. = LC_X26_Y9_N3; Fanout = 2; COMB Node = 'Equal2~99'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.146 ns" { \GenSpkS:Count11[4] Equal2~99 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 350 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.442 ns) 1.998 ns Equal2~101 3 COMB LC_X26_Y9_N1 11 " "Info: 3: + IC(0.410 ns) + CELL(0.442 ns) = 1.998 ns; Loc. = LC_X26_Y9_N1; Fanout = 11; COMB Node = 'Equal2~101'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.852 ns" { Equal2~99 Equal2~101 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 350 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(1.225 ns) 4.508 ns \\GenSpkS:Count11\[8\] 4 REG LC_X26_Y8_N3 5 " "Info: 4: + IC(1.285 ns) + CELL(1.225 ns) = 4.508 ns; Loc. = LC_X26_Y8_N3; Fanout = 5; REG Node = '\\GenSpkS:Count11\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.510 ns" { Equal2~101 \GenSpkS:Count11[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.257 ns ( 50.07 % ) " "Info: Total cell delay = 2.257 ns ( 50.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.251 ns ( 49.93 % ) " "Info: Total interconnect delay = 2.251 ns ( 49.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.508 ns" { \GenSpkS:Count11[4] Equal2~99 Equal2~101 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.508 ns" { \GenSpkS:Count11[4] Equal2~99 Equal2~101 \GenSpkS:Count11[8] } { 0.000ns 0.556ns 0.410ns 1.285ns } { 0.000ns 0.590ns 0.442ns 1.225ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.959 ns - Smallest " "Info: - Smallest clock skew is -0.959 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 5.295 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 5.295 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK1 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.935 ns) 3.444 ns Count4\[2\] 2 REG LC_X26_Y8_N6 3 " "Info: 2: + IC(1.040 ns) + CELL(0.935 ns) = 3.444 ns; Loc. = LC_X26_Y8_N6; Fanout = 3; REG Node = 'Count4\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.975 ns" { CLK1 Count4[2] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.543 ns) + CELL(0.114 ns) 4.101 ns LessThan4~39 3 COMB LC_X26_Y8_N8 16 " "Info: 3: + IC(0.543 ns) + CELL(0.114 ns) = 4.101 ns; Loc. = LC_X26_Y8_N8; Fanout = 16; COMB Node = 'LessThan4~39'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.657 ns" { Count4[2] LessThan4~39 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.483 ns) + CELL(0.711 ns) 5.295 ns \\GenSpkS:Count11\[8\] 4 REG LC_X26_Y8_N3 5 " "Info: 4: + IC(0.483 ns) + CELL(0.711 ns) = 5.295 ns; Loc. = LC_X26_Y8_N3; Fanout = 5; REG Node = '\\GenSpkS:Count11\[8\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.194 ns" { LessThan4~39 \GenSpkS:Count11[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns ( 60.98 % ) " "Info: Total cell delay = 3.229 ns ( 60.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.066 ns ( 39.02 % ) " "Info: Total interconnect delay = 2.066 ns ( 39.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.295 ns" { CLK1 Count4[2] LessThan4~39 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.295 ns" { CLK1 CLK1~out0 Count4[2] LessThan4~39 \GenSpkS:Count11[8] } { 0.000ns 0.000ns 1.040ns 0.543ns 0.483ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 6.254 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 6.254 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK1 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.935 ns) 3.444 ns Count4\[3\] 2 REG LC_X26_Y8_N7 2 " "Info: 2: + IC(1.040 ns) + CELL(0.935 ns) = 3.444 ns; Loc. = LC_X26_Y8_N7; Fanout = 2; REG Node = 'Count4\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.975 ns" { CLK1 Count4[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.556 ns) + CELL(0.292 ns) 4.292 ns LessThan4~39 3 COMB LC_X26_Y8_N8 16 " "Info: 3: + IC(0.556 ns) + CELL(0.292 ns) = 4.292 ns; Loc. = LC_X26_Y8_N8; Fanout = 16; COMB Node = 'LessThan4~39'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.848 ns" { Count4[3] LessThan4~39 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.251 ns) + CELL(0.711 ns) 6.254 ns \\GenSpkS:Count11\[4\] 4 REG LC_X26_Y9_N9 3 " "Info: 4: + IC(1.251 ns) + CELL(0.711 ns) = 6.254 ns; Loc. = LC_X26_Y9_N9; Fanout = 3; REG Node = '\\GenSpkS:Count11\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.962 ns" { LessThan4~39 \GenSpkS:Count11[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns ( 54.48 % ) " "Info: Total cell delay = 3.407 ns ( 54.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.847 ns ( 45.52 % ) " "Info: Total interconnect delay = 2.847 ns ( 45.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.254 ns" { CLK1 Count4[3] LessThan4~39 \GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.254 ns" { CLK1 CLK1~out0 Count4[3] LessThan4~39 \GenSpkS:Count11[4] } { 0.000ns 0.000ns 1.040ns 0.556ns 1.251ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.295 ns" { CLK1 Count4[2] LessThan4~39 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.295 ns" { CLK1 CLK1~out0 Count4[2] LessThan4~39 \GenSpkS:Count11[8] } { 0.000ns 0.000ns 1.040ns 0.543ns 0.483ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.254 ns" { CLK1 Count4[3] LessThan4~39 \GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.254 ns" { CLK1 CLK1~out0 Count4[3] LessThan4~39 \GenSpkS:Count11[4] } { 0.000ns 0.000ns 1.040ns 0.556ns 1.251ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.508 ns" { \GenSpkS:Count11[4] Equal2~99 Equal2~101 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "4.508 ns" { \GenSpkS:Count11[4] Equal2~99 Equal2~101 \GenSpkS:Count11[8] } { 0.000ns 0.556ns 0.410ns 1.285ns } { 0.000ns 0.590ns 0.442ns 1.225ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.295 ns" { CLK1 Count4[2] LessThan4~39 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "5.295 ns" { CLK1 CLK1~out0 Count4[2] LessThan4~39 \GenSpkS:Count11[8] } { 0.000ns 0.000ns 1.040ns 0.543ns 0.483ns } { 0.000ns 1.469ns 0.935ns 0.114ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.254 ns" { CLK1 Count4[3] LessThan4~39 \GenSpkS:Count11[4] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.254 ns" { CLK1 CLK1~out0 Count4[3] LessThan4~39 \GenSpkS:Count11[4] } { 0.000ns 0.000ns 1.040ns 0.556ns 1.251ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 51 " "Warning: Circuit may not operate. Detected 51 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "m2_state.m2_st8 m2_nexts.m2_st9 clk 1.729 ns " "Info: Found hold time violation between source  pin or register \"m2_state.m2_st8\" and destination pin or register \"m2_nexts.m2_st9\" for clock \"clk\" (Hold time is 1.729 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.601 ns + Largest " "Info: + Largest clock skew is 2.601 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.171 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.171 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.935 ns) 4.094 ns ps2_clk_r 2 REG LC_X22_Y8_N9 84 " "Info: 2: + IC(1.690 ns) + CELL(0.935 ns) = 4.094 ns; Loc. = LC_X22_Y8_N9; Fanout = 84; REG Node = 'ps2_clk_r'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.625 ns" { clk ps2_clk_r } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.711 ns) 6.171 ns m2_nexts.m2_st9 3 REG LC_X23_Y9_N9 1 " "Info: 3: + IC(1.366 ns) + CELL(0.711 ns) = 6.171 ns; Loc. = LC_X23_Y9_N9; Fanout = 1; REG Node = 'm2_nexts.m2_st9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.077 ns" { ps2_clk_r m2_nexts.m2_st9 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 50.48 % ) " "Info: Total cell delay = 3.115 ns ( 50.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.056 ns ( 49.52 % ) " "Info: Total interconnect delay = 3.056 ns ( 49.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.171 ns" { clk ps2_clk_r m2_nexts.m2_st9 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.171 ns" { clk clk~out0 ps2_clk_r m2_nexts.m2_st9 } { 0.000ns 0.000ns 1.690ns 1.366ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.570 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.570 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.390 ns) + CELL(0.711 ns) 3.570 ns m2_state.m2_st8 2 REG LC_X23_Y9_N2 2 " "Info: 2: + IC(1.390 ns) + CELL(0.711 ns) = 3.570 ns; Loc. = LC_X23_Y9_N2; Fanout = 2; REG Node = 'm2_state.m2_st8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.101 ns" { clk m2_state.m2_st8 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 61.06 % ) " "Info: Total cell delay = 2.180 ns ( 61.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.390 ns ( 38.94 % ) " "Info: Total interconnect delay = 1.390 ns ( 38.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.570 ns" { clk m2_state.m2_st8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.570 ns" { clk clk~out0 m2_state.m2_st8 } { 0.000ns 0.000ns 1.390ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.171 ns" { clk ps2_clk_r m2_nexts.m2_st9 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.171 ns" { clk clk~out0 ps2_clk_r m2_nexts.m2_st9 } { 0.000ns 0.000ns 1.690ns 1.366ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.570 ns" { clk m2_state.m2_st8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.570 ns" { clk clk~out0 m2_state.m2_st8 } { 0.000ns 0.000ns 1.390ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 146 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.663 ns - Shortest register register " "Info: - Shortest register to register delay is 0.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m2_state.m2_st8 1 REG LC_X23_Y9_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y9_N2; Fanout = 2; REG Node = 'm2_state.m2_st8'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { m2_state.m2_st8 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 146 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.115 ns) 0.663 ns m2_nexts.m2_st9 2 REG LC_X23_Y9_N9 1 " "Info: 2: + IC(0.548 ns) + CELL(0.115 ns) = 0.663 ns; Loc. = LC_X23_Y9_N9; Fanout = 1; REG Node = 'm2_nexts.m2_st9'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { m2_state.m2_st8 m2_nexts.m2_st9 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.35 % ) " "Info: Total cell delay = 0.115 ns ( 17.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.548 ns ( 82.65 % ) " "Info: Total interconnect delay = 0.548 ns ( 82.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { m2_state.m2_st8 m2_nexts.m2_st9 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.663 ns" { m2_state.m2_st8 m2_nexts.m2_st9 } { 0.000ns 0.548ns } { 0.000ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.171 ns" { clk ps2_clk_r m2_nexts.m2_st9 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.171 ns" { clk clk~out0 ps2_clk_r m2_nexts.m2_st9 } { 0.000ns 0.000ns 1.690ns 1.366ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.570 ns" { clk m2_state.m2_st8 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.570 ns" { clk clk~out0 m2_state.m2_st8 } { 0.000ns 0.000ns 1.390ns } { 0.000ns 1.469ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.663 ns" { m2_state.m2_st8 m2_nexts.m2_st9 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "0.663 ns" { m2_state.m2_st8 m2_nexts.m2_st9 } { 0.000ns 0.548ns } { 0.000ns 0.115ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}