ps2_mouse9.tan.qmsg

PS2键盘鼠标接口控制实现电子琴功能

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK1 " "Info: Assuming node \"CLK1\" is an undefined clock" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 7 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Count4\[2\] " "Info: Detected ripple clock \"Count4\[2\]\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Count4\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Count4\[3\] " "Info: Detected ripple clock \"Count4\[3\]\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "Count4\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan4~39 " "Info: Detected gated clock \"LessThan4~39\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "LessThan4~39" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FullSpkS " "Info: Detected ripple clock \"FullSpkS\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 44 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "FullSpkS" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ps2_clk_r " "Info: Detected ripple clock \"ps2_clk_r\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ps2_clk_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ps2:uA\|ps2_clk_r " "Info: Detected ripple clock \"ps2:uA\|ps2_clk_r\" as buffer" {  } { { "ps2.vhd" "" { Text "D:/Ps2-ALL/ps2.vhd" 32 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ps2:uA\|ps2_clk_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[3\] register q_data2_x\[3\] 135.39 MHz 7.386 ns Internal " "Info: Clock \"clk\" has Internal fmax of 135.39 MHz between source register \"count\[3\]\" and destination register \"q_data2_x\[3\]\" (period= 7.386 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.481 ns + Longest register register " "Info: + Longest register to register delay is 3.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[3\] 1 REG LC_X21_Y8_N0 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X21_Y8_N0; Fanout = 6; REG Node = 'count\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { count[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.507 ns) + CELL(0.442 ns) 0.949 ns LessThan3~41 2 COMB LC_X21_Y8_N8 49 " "Info: 2: + IC(0.507 ns) + CELL(0.442 ns) = 0.949 ns; Loc. = LC_X21_Y8_N8; Fanout = 49; COMB Node = 'LessThan3~41'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.949 ns" { count[3] LessThan3~41 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1509 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.114 ns) 1.839 ns q_data2_x\[8\]~0 3 COMB LC_X20_Y8_N2 8 " "Info: 3: + IC(0.776 ns) + CELL(0.114 ns) = 1.839 ns; Loc. = LC_X20_Y8_N2; Fanout = 8; COMB Node = 'q_data2_x\[8\]~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.890 ns" { LessThan3~41 q_data2_x[8]~0 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.867 ns) 3.481 ns q_data2_x\[3\] 4 REG LC_X19_Y8_N2 2 " "Info: 4: + IC(0.775 ns) + CELL(0.867 ns) = 3.481 ns; Loc. = LC_X19_Y8_N2; Fanout = 2; REG Node = 'q_data2_x\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.642 ns" { q_data2_x[8]~0 q_data2_x[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.423 ns ( 40.88 % ) " "Info: Total cell delay = 1.423 ns ( 40.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.058 ns ( 59.12 % ) " "Info: Total interconnect delay = 2.058 ns ( 59.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.481 ns" { count[3] LessThan3~41 q_data2_x[8]~0 q_data2_x[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.481 ns" { count[3] LessThan3~41 q_data2_x[8]~0 q_data2_x[3] } { 0.000ns 0.507ns 0.776ns 0.775ns } { 0.000ns 0.442ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.049 ns - Smallest " "Info: - Smallest clock skew is 0.049 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.085 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.085 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.935 ns) 4.094 ns ps2_clk_r 2 REG LC_X22_Y8_N9 84 " "Info: 2: + IC(1.690 ns) + CELL(0.935 ns) = 4.094 ns; Loc. = LC_X22_Y8_N9; Fanout = 84; REG Node = 'ps2_clk_r'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.625 ns" { clk ps2_clk_r } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.280 ns) + CELL(0.711 ns) 6.085 ns q_data2_x\[3\] 3 REG LC_X19_Y8_N2 2 " "Info: 3: + IC(1.280 ns) + CELL(0.711 ns) = 6.085 ns; Loc. = LC_X19_Y8_N2; Fanout = 2; REG Node = 'q_data2_x\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.991 ns" { ps2_clk_r q_data2_x[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 51.19 % ) " "Info: Total cell delay = 3.115 ns ( 51.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.970 ns ( 48.81 % ) " "Info: Total interconnect delay = 2.970 ns ( 48.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.085 ns" { clk ps2_clk_r q_data2_x[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.085 ns" { clk clk~out0 ps2_clk_r q_data2_x[3] } { 0.000ns 0.000ns 1.690ns 1.280ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.036 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.036 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_93 57 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.690 ns) + CELL(0.935 ns) 4.094 ns ps2_clk_r 2 REG LC_X22_Y8_N9 84 " "Info: 2: + IC(1.690 ns) + CELL(0.935 ns) = 4.094 ns; Loc. = LC_X22_Y8_N9; Fanout = 84; REG Node = 'ps2_clk_r'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.625 ns" { clk ps2_clk_r } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.711 ns) 6.036 ns count\[3\] 3 REG LC_X21_Y8_N0 6 " "Info: 3: + IC(1.231 ns) + CELL(0.711 ns) = 6.036 ns; Loc. = LC_X21_Y8_N0; Fanout = 6; REG Node = 'count\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.942 ns" { ps2_clk_r count[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 51.61 % ) " "Info: Total cell delay = 3.115 ns ( 51.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.921 ns ( 48.39 % ) " "Info: Total interconnect delay = 2.921 ns ( 48.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.036 ns" { clk ps2_clk_r count[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.036 ns" { clk clk~out0 ps2_clk_r count[3] } { 0.000ns 0.000ns 1.690ns 1.231ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.085 ns" { clk ps2_clk_r q_data2_x[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.085 ns" { clk clk~out0 ps2_clk_r q_data2_x[3] } { 0.000ns 0.000ns 1.690ns 1.280ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.036 ns" { clk ps2_clk_r count[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.036 ns" { clk clk~out0 ps2_clk_r count[3] } { 0.000ns 0.000ns 1.690ns 1.231ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } } { "ps2_mouse9.vhd" "" { Text "D:/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.481 ns" { count[3] LessThan3~41 q_data2_x[8]~0 q_data2_x[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "3.481 ns" { count[3] LessThan3~41 q_data2_x[8]~0 q_data2_x[3] } { 0.000ns 0.507ns 0.776ns 0.775ns } { 0.000ns 0.442ns 0.114ns 0.867ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.085 ns" { clk ps2_clk_r q_data2_x[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.085 ns" { clk clk~out0 ps2_clk_r q_data2_x[3] } { 0.000ns 0.000ns 1.690ns 1.280ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.036 ns" { clk ps2_clk_r count[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.036 ns" { clk clk~out0 ps2_clk_r count[3] } { 0.000ns 0.000ns 1.690ns 1.231ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}