prev_cmp_ps2_mouse9.tan.qmsg

PS2键盘鼠标接口控制实现电子琴功能

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK1 register \\GenSpkS:Count11\[1\] register \\GenSpkS:Count11\[8\] 187.37 MHz 5.337 ns Internal " "Info: Clock \"CLK1\" has Internal fmax of 187.37 MHz between source register \"\\GenSpkS:Count11\[1\]\" and destination register \"\\GenSpkS:Count11\[8\]\" (period= 5.337 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.130 ns + Longest register register " "Info: + Longest register to register delay is 4.130 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\GenSpkS:Count11\[1\] 1 REG LC_X11_Y12_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y12_N6; Fanout = 4; REG Node = '\\GenSpkS:Count11\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { \GenSpkS:Count11[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.590 ns) 1.128 ns Equal2~98 2 COMB LC_X11_Y12_N2 2 " "Info: 2: + IC(0.538 ns) + CELL(0.590 ns) = 1.128 ns; Loc. = LC_X11_Y12_N2; Fanout = 2; COMB Node = 'Equal2~98'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.128 ns" { \GenSpkS:Count11[1] Equal2~98 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 350 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.197 ns) + CELL(0.114 ns) 2.439 ns Equal2~101 3 COMB LC_X11_Y11_N8 11 " "Info: 3: + IC(1.197 ns) + CELL(0.114 ns) = 2.439 ns; Loc. = LC_X11_Y11_N8; Fanout = 11; COMB Node = 'Equal2~101'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.311 ns" { Equal2~98 Equal2~101 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 350 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.466 ns) + CELL(1.225 ns) 4.130 ns \\GenSpkS:Count11\[8\] 4 REG LC_X11_Y11_N3 5 " "Info: 4: + IC(0.466 ns) + CELL(1.225 ns) = 4.130 ns; Loc. = LC_X11_Y11_N3; Fanout = 5; REG Node = '\\GenSpkS:Count11\[8\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.691 ns" { Equal2~101 \GenSpkS:Count11[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.929 ns ( 46.71 % ) " "Info: Total cell delay = 1.929 ns ( 46.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.201 ns ( 53.29 % ) " "Info: Total interconnect delay = 2.201 ns ( 53.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.130 ns" { \GenSpkS:Count11[1] Equal2~98 Equal2~101 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.130 ns" { \GenSpkS:Count11[1] {} Equal2~98 {} Equal2~101 {} \GenSpkS:Count11[8] {} } { 0.000ns 0.538ns 1.197ns 0.466ns } { 0.000ns 0.590ns 0.114ns 1.225ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.946 ns - Smallest " "Info: - Smallest clock skew is -0.946 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 destination 6.246 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK1\" to destination register is 6.246 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK1 1 CLK PIN_128 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_128; Fanout = 4; CLK Node = 'CLK1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.935 ns) 3.684 ns Count4\[3\] 2 REG LC_X11_Y13_N3 2 " "Info: 2: + IC(1.274 ns) + CELL(0.935 ns) = 3.684 ns; Loc. = LC_X11_Y13_N3; Fanout = 2; REG Node = 'Count4\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { CLK1 Count4[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.269 ns) + CELL(0.114 ns) 5.067 ns LessThan4 3 COMB LC_X11_Y11_N6 16 " "Info: 3: + IC(1.269 ns) + CELL(0.114 ns) = 5.067 ns; Loc. = LC_X11_Y11_N6; Fanout = 16; COMB Node = 'LessThan4'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.383 ns" { Count4[3] LessThan4 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.468 ns) + CELL(0.711 ns) 6.246 ns \\GenSpkS:Count11\[8\] 4 REG LC_X11_Y11_N3 5 " "Info: 4: + IC(0.468 ns) + CELL(0.711 ns) = 6.246 ns; Loc. = LC_X11_Y11_N3; Fanout = 5; REG Node = '\\GenSpkS:Count11\[8\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { LessThan4 \GenSpkS:Count11[8] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.235 ns ( 51.79 % ) " "Info: Total cell delay = 3.235 ns ( 51.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.011 ns ( 48.21 % ) " "Info: Total interconnect delay = 3.011 ns ( 48.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.246 ns" { CLK1 Count4[3] LessThan4 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.246 ns" { CLK1 {} CLK1~out0 {} Count4[3] {} LessThan4 {} \GenSpkS:Count11[8] {} } { 0.000ns 0.000ns 1.274ns 1.269ns 0.468ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK1 source 7.192 ns - Longest register " "Info: - Longest clock path from clock \"CLK1\" to source register is 7.192 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns CLK1 1 CLK PIN_128 4 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_128; Fanout = 4; CLK Node = 'CLK1'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK1 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.935 ns) 3.684 ns Count4\[2\] 2 REG LC_X11_Y13_N2 3 " "Info: 2: + IC(1.274 ns) + CELL(0.935 ns) = 3.684 ns; Loc. = LC_X11_Y13_N2; Fanout = 3; REG Node = 'Count4\[2\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { CLK1 Count4[2] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.281 ns) + CELL(0.292 ns) 5.257 ns LessThan4 3 COMB LC_X11_Y11_N6 16 " "Info: 3: + IC(1.281 ns) + CELL(0.292 ns) = 5.257 ns; Loc. = LC_X11_Y11_N6; Fanout = 16; COMB Node = 'LessThan4'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.573 ns" { Count4[2] LessThan4 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.224 ns) + CELL(0.711 ns) 7.192 ns \\GenSpkS:Count11\[1\] 4 REG LC_X11_Y12_N6 4 " "Info: 4: + IC(1.224 ns) + CELL(0.711 ns) = 7.192 ns; Loc. = LC_X11_Y12_N6; Fanout = 4; REG Node = '\\GenSpkS:Count11\[1\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.935 ns" { LessThan4 \GenSpkS:Count11[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.413 ns ( 47.46 % ) " "Info: Total cell delay = 3.413 ns ( 47.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.779 ns ( 52.54 % ) " "Info: Total interconnect delay = 3.779 ns ( 52.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.192 ns" { CLK1 Count4[2] LessThan4 \GenSpkS:Count11[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.192 ns" { CLK1 {} CLK1~out0 {} Count4[2] {} LessThan4 {} \GenSpkS:Count11[1] {} } { 0.000ns 0.000ns 1.274ns 1.281ns 1.224ns } { 0.000ns 1.475ns 0.935ns 0.292ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.246 ns" { CLK1 Count4[3] LessThan4 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.246 ns" { CLK1 {} CLK1~out0 {} Count4[3] {} LessThan4 {} \GenSpkS:Count11[8] {} } { 0.000ns 0.000ns 1.274ns 1.269ns 0.468ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.192 ns" { CLK1 Count4[2] LessThan4 \GenSpkS:Count11[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.192 ns" { CLK1 {} CLK1~out0 {} Count4[2] {} LessThan4 {} \GenSpkS:Count11[1] {} } { 0.000ns 0.000ns 1.274ns 1.281ns 1.224ns } { 0.000ns 1.475ns 0.935ns 0.292ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.130 ns" { \GenSpkS:Count11[1] Equal2~98 Equal2~101 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.130 ns" { \GenSpkS:Count11[1] {} Equal2~98 {} Equal2~101 {} \GenSpkS:Count11[8] {} } { 0.000ns 0.538ns 1.197ns 0.466ns } { 0.000ns 0.590ns 0.114ns 1.225ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.246 ns" { CLK1 Count4[3] LessThan4 \GenSpkS:Count11[8] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.246 ns" { CLK1 {} CLK1~out0 {} Count4[3] {} LessThan4 {} \GenSpkS:Count11[8] {} } { 0.000ns 0.000ns 1.274ns 1.269ns 0.468ns } { 0.000ns 1.475ns 0.935ns 0.114ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.192 ns" { CLK1 Count4[2] LessThan4 \GenSpkS:Count11[1] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.192 ns" { CLK1 {} CLK1~out0 {} Count4[2] {} LessThan4 {} \GenSpkS:Count11[1] {} } { 0.000ns 0.000ns 1.274ns 1.281ns 1.224ns } { 0.000ns 1.475ns 0.935ns 0.292ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 53 " "Warning: Circuit may not operate. Detected 53 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "m2_state.m2_st17 m2_nexts.m2_st18 clk 1.461 ns " "Info: Found hold time violation between source  pin or register \"m2_state.m2_st17\" and destination pin or register \"m2_nexts.m2_st18\" for clock \"clk\" (Hold time is 1.461 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.327 ns + Largest " "Info: + Largest clock skew is 2.327 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.856 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 5.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 57 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.935 ns) 3.791 ns ps2_clk_r 2 REG LC_X18_Y11_N7 84 " "Info: 2: + IC(1.381 ns) + CELL(0.935 ns) = 3.791 ns; Loc. = LC_X18_Y11_N7; Fanout = 84; REG Node = 'ps2_clk_r'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.316 ns" { clk ps2_clk_r } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.354 ns) + CELL(0.711 ns) 5.856 ns m2_nexts.m2_st18 3 REG LC_X17_Y12_N7 1 " "Info: 3: + IC(1.354 ns) + CELL(0.711 ns) = 5.856 ns; Loc. = LC_X17_Y12_N7; Fanout = 1; REG Node = 'm2_nexts.m2_st18'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.065 ns" { ps2_clk_r m2_nexts.m2_st18 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 53.30 % ) " "Info: Total cell delay = 3.121 ns ( 53.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.735 ns ( 46.70 % ) " "Info: Total interconnect delay = 2.735 ns ( 46.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.856 ns" { clk ps2_clk_r m2_nexts.m2_st18 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.856 ns" { clk {} clk~out0 {} ps2_clk_r {} m2_nexts.m2_st18 {} } { 0.000ns 0.000ns 1.381ns 1.354ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.529 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 57 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.343 ns) + CELL(0.711 ns) 3.529 ns m2_state.m2_st17 2 REG LC_X17_Y12_N8 2 " "Info: 2: + IC(1.343 ns) + CELL(0.711 ns) = 3.529 ns; Loc. = LC_X17_Y12_N8; Fanout = 2; REG Node = 'm2_state.m2_st17'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.054 ns" { clk m2_state.m2_st17 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.186 ns ( 61.94 % ) " "Info: Total cell delay = 2.186 ns ( 61.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.343 ns ( 38.06 % ) " "Info: Total interconnect delay = 1.343 ns ( 38.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.529 ns" { clk m2_state.m2_st17 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.529 ns" { clk {} clk~out0 {} m2_state.m2_st17 {} } { 0.000ns 0.000ns 1.343ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.856 ns" { clk ps2_clk_r m2_nexts.m2_st18 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.856 ns" { clk {} clk~out0 {} ps2_clk_r {} m2_nexts.m2_st18 {} } { 0.000ns 0.000ns 1.381ns 1.354ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.529 ns" { clk m2_state.m2_st17 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.529 ns" { clk {} clk~out0 {} m2_state.m2_st17 {} } { 0.000ns 0.000ns 1.343ns } { 0.000ns 1.475ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.657 ns - Shortest register register " "Info: - Shortest register to register delay is 0.657 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m2_state.m2_st17 1 REG LC_X17_Y12_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y12_N8; Fanout = 2; REG Node = 'm2_state.m2_st17'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { m2_state.m2_st17 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.115 ns) 0.657 ns m2_nexts.m2_st18 2 REG LC_X17_Y12_N7 1 " "Info: 2: + IC(0.542 ns) + CELL(0.115 ns) = 0.657 ns; Loc. = LC_X17_Y12_N7; Fanout = 1; REG Node = 'm2_nexts.m2_st18'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.657 ns" { m2_state.m2_st17 m2_nexts.m2_st18 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.50 % ) " "Info: Total cell delay = 0.115 ns ( 17.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.542 ns ( 82.50 % ) " "Info: Total interconnect delay = 0.542 ns ( 82.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.657 ns" { m2_state.m2_st17 m2_nexts.m2_st18 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.657 ns" { m2_state.m2_st17 {} m2_nexts.m2_st18 {} } { 0.000ns 0.542ns } { 0.000ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 74 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.856 ns" { clk ps2_clk_r m2_nexts.m2_st18 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.856 ns" { clk {} clk~out0 {} ps2_clk_r {} m2_nexts.m2_st18 {} } { 0.000ns 0.000ns 1.381ns 1.354ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.529 ns" { clk m2_state.m2_st17 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.529 ns" { clk {} clk~out0 {} m2_state.m2_st17 {} } { 0.000ns 0.000ns 1.343ns } { 0.000ns 1.475ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.657 ns" { m2_state.m2_st17 m2_nexts.m2_st18 } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "0.657 ns" { m2_state.m2_st17 {} m2_nexts.m2_st18 {} } { 0.000ns 0.542ns } { 0.000ns 0.115ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}