prev_cmp_ps2_mouse9.tan.qmsg

PS2键盘鼠标接口控制实现电子琴功能

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK1 " "Info: Assuming node \"CLK1\" is an undefined clock" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 7 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "Count4\[3\] " "Info: Detected ripple clock \"Count4\[3\]\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Count4\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "Count4\[2\] " "Info: Detected ripple clock \"Count4\[2\]\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "Count4\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "LessThan4 " "Info: Detected gated clock \"LessThan4\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 342 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "LessThan4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "FullSpkS " "Info: Detected ripple clock \"FullSpkS\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 44 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "FullSpkS" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ps2_clk_r " "Info: Detected ripple clock \"ps2_clk_r\" as buffer" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ps2_clk_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ps2:uA\|ps2_clk_r " "Info: Detected ripple clock \"ps2:uA\|ps2_clk_r\" as buffer" {  } { { "ps2.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2.vhd" 32 -1 0 } } { "d:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "ps2:uA\|ps2_clk_r" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[3\] register q_data2\[7\] 115.58 MHz 8.652 ns Internal " "Info: Clock \"clk\" has Internal fmax of 115.58 MHz between source register \"count\[3\]\" and destination register \"q_data2\[7\]\" (period= 8.652 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.173 ns + Longest register register " "Info: + Longest register to register delay is 3.173 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[3\] 1 REG LC_X17_Y10_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y10_N4; Fanout = 6; REG Node = 'count\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.582 ns) + CELL(0.442 ns) 1.024 ns q_data2\[7\]~324 2 COMB LC_X17_Y10_N9 8 " "Info: 2: + IC(0.582 ns) + CELL(0.442 ns) = 1.024 ns; Loc. = LC_X17_Y10_N9; Fanout = 8; COMB Node = 'q_data2\[7\]~324'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.024 ns" { count[3] q_data2[7]~324 } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.282 ns) + CELL(0.867 ns) 3.173 ns q_data2\[7\] 3 REG LC_X18_Y11_N9 4 " "Info: 3: + IC(1.282 ns) + CELL(0.867 ns) = 3.173 ns; Loc. = LC_X18_Y11_N9; Fanout = 4; REG Node = 'q_data2\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.149 ns" { q_data2[7]~324 q_data2[7] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.309 ns ( 41.25 % ) " "Info: Total cell delay = 1.309 ns ( 41.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.864 ns ( 58.75 % ) " "Info: Total interconnect delay = 1.864 ns ( 58.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { count[3] q_data2[7]~324 q_data2[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.173 ns" { count[3] {} q_data2[7]~324 {} q_data2[7] {} } { 0.000ns 0.582ns 1.282ns } { 0.000ns 0.442ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.892 ns - Smallest " "Info: - Smallest clock skew is -0.892 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.068 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.068 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 57 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.935 ns) 3.791 ns ps2_clk_r 2 REG LC_X18_Y11_N7 84 " "Info: 2: + IC(1.381 ns) + CELL(0.935 ns) = 3.791 ns; Loc. = LC_X18_Y11_N7; Fanout = 84; REG Node = 'ps2_clk_r'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.316 ns" { clk ps2_clk_r } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.566 ns) + CELL(0.711 ns) 5.068 ns q_data2\[7\] 3 REG LC_X18_Y11_N9 4 " "Info: 3: + IC(0.566 ns) + CELL(0.711 ns) = 5.068 ns; Loc. = LC_X18_Y11_N9; Fanout = 4; REG Node = 'q_data2\[7\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.277 ns" { ps2_clk_r q_data2[7] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 61.58 % ) " "Info: Total cell delay = 3.121 ns ( 61.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.947 ns ( 38.42 % ) " "Info: Total interconnect delay = 1.947 ns ( 38.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.068 ns" { clk ps2_clk_r q_data2[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.068 ns" { clk {} clk~out0 {} ps2_clk_r {} q_data2[7] {} } { 0.000ns 0.000ns 1.381ns 0.566ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.960 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.960 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_123 57 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_123; Fanout = 57; CLK Node = 'clk'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.381 ns) + CELL(0.935 ns) 3.791 ns ps2_clk_r 2 REG LC_X18_Y11_N7 84 " "Info: 2: + IC(1.381 ns) + CELL(0.935 ns) = 3.791 ns; Loc. = LC_X18_Y11_N7; Fanout = 84; REG Node = 'ps2_clk_r'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.316 ns" { clk ps2_clk_r } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.458 ns) + CELL(0.711 ns) 5.960 ns count\[3\] 3 REG LC_X17_Y10_N4 6 " "Info: 3: + IC(1.458 ns) + CELL(0.711 ns) = 5.960 ns; Loc. = LC_X17_Y10_N4; Fanout = 6; REG Node = 'count\[3\]'" {  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.169 ns" { ps2_clk_r count[3] } "NODE_NAME" } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 52.37 % ) " "Info: Total cell delay = 3.121 ns ( 52.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.839 ns ( 47.63 % ) " "Info: Total interconnect delay = 2.839 ns ( 47.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.960 ns" { clk ps2_clk_r count[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.960 ns" { clk {} clk~out0 {} ps2_clk_r {} count[3] {} } { 0.000ns 0.000ns 1.381ns 1.458ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.068 ns" { clk ps2_clk_r q_data2[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.068 ns" { clk {} clk~out0 {} ps2_clk_r {} q_data2[7] {} } { 0.000ns 0.000ns 1.381ns 0.566ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.960 ns" { clk ps2_clk_r count[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.960 ns" { clk {} clk~out0 {} ps2_clk_r {} count[3] {} } { 0.000ns 0.000ns 1.381ns 1.458ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 135 -1 0 } } { "ps2_mouse9.vhd" "" { Text "D:/fpgaprjs/Ps2-ALL/ps2_mouse9.vhd" 153 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.173 ns" { count[3] q_data2[7]~324 q_data2[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "3.173 ns" { count[3] {} q_data2[7]~324 {} q_data2[7] {} } { 0.000ns 0.582ns 1.282ns } { 0.000ns 0.442ns 0.867ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.068 ns" { clk ps2_clk_r q_data2[7] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.068 ns" { clk {} clk~out0 {} ps2_clk_r {} q_data2[7] {} } { 0.000ns 0.000ns 1.381ns 0.566ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } } { "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.960 ns" { clk ps2_clk_r count[3] } "NODE_NAME" } } { "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/80/quartus/bin/Technology_Viewer.qrui" "5.960 ns" { clk {} clk~out0 {} ps2_clk_r {} count[3] {} } { 0.000ns 0.000ns 1.381ns 1.458ns } { 0.000ns 1.475ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}