ps2_mouse9.tan.rpt

来自「PS2键盘鼠标接口控制实现电子琴功能」· RPT 代码 · 共 329 行 · 第 1/5 页

Timing Analyzer report for ps2_mouse9
Tue May 19 19:06:27 2009
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Setup: 'CLK1'
  7. Clock Hold: 'clk'
  8. tsu
  9. tco
 10. tpd
 11. th
 12. Minimum tco
 13. Minimum tpd
 14. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                        ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+----------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                ; To                   ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+----------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 10.836 ns                        ; reset               ; \GenSpkS:Count11[8]  ; --         ; CLK1     ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 16.479 ns                        ; q_data2[3]          ; CODE1[3]             ; clk        ; --       ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 18.089 ns                        ; reset               ; CODE1[1]             ; --         ; --       ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; -2.941 ns                        ; ps2_data            ; q_data1_x[8]         ; --         ; clk      ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 7.618 ns                         ; ps2_clk_s           ; ps2_clk00            ; clk        ; --       ; 0            ;
; Worst-case Minimum tpd       ; N/A                                      ; None          ; 13.074 ns                        ; reset               ; ps2_data3A[2]        ; --         ; --       ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 135.39 MHz ( period = 7.386 ns ) ; count[3]            ; q_data2_x[1]         ; clk        ; clk      ; 0            ;
; Clock Setup: 'CLK1'          ; N/A                                      ; None          ; 174.58 MHz ( period = 5.728 ns ) ; \GenSpkS:Count11[4] ; \GenSpkS:Count11[10] ; CLK1       ; CLK1     ; 0            ;
; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; m2_state.m2_st8     ; m2_nexts.m2_st9      ; clk        ; clk      ; 51           ;
; Total number of failed paths ;                                          ;               ;                                  ;                     ;                      ;            ;          ; 51           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+---------------------+----------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;