wuxian.hif

串口8位数据 verilog hdl提取

Version 7.2 Build 151 09/26/2007 SJ Full Version
11
1012
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
int_div
# storage
db|wuxian.(2).cnf
db|wuxian.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
int_div.v
ee7fb1abc724ae13d6e7a596a0406a71
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
diver
24000000
PARAMETER_UNKNOWN
USR
div_width
25
PARAMETER_UNKNOWN
USR
}
# hierarchies {
int_div:inst1
}
# lmf
..|..|quartus2|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
wuxian
# storage
db|wuxian.(1).cnf
db|wuxian.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
wuxian.v
427cccc2e37c1ca370fe53a4b07f56b9
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
wuxian:inst
}
# lmf
..|..|quartus2|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
wuxian_test
# storage
db|wuxian.(0).cnf
db|wuxian.(0).cnf
# case_insensitive
# source_file
wuxian_test.bdf
4f7ce72272d2bb3291deef5a135bf0
25
# internal_option {
BLOCK_DESIGN_NAMING
OFF
}
# hierarchies {
|
}
# lmf
..|..|quartus2|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete