wuxian.v

串口8位数据 verilog hdl提取

module wuxian(d,clear,dout,clk,led);
input d;
input clear;
input clk;
output[7:0] dout;
output[7:0] led;
reg[7:0] dout_r,led_r;
reg[3:0] add;

assign led=led_r;
assign dout=dout_r;

always@(posedge clk)
  begin 
  if(clear) 
          begin
          dout_r=8'd0;
          add=4'd0; 
          end
          
  else   
        if(add==4'b1000) 
         begin
        led_r=dout_r; 
         add=4'b0000;
         dout_r=8'd0;
         end 
       else  begin 
         dout_r=dout_r<<1;
         dout_r[0]=d;
         add=add+1'b1;  
         end
         
end     
endmodule