_csl_ccdcchecksettings.c

TI达芬奇dm644x各硬件模块测试代码

/** @file _csl_ccdcCheckSettings.c
 *
 *  @brief    File for functional layer of CSL API @a CSL_ccdcCheckSettings()
 *
 *  Description
 *    - The @a CSL_ccdcCheckSettings() function definition & it's associated
 *      functions
 *
 *  @date 6th June, 2005
 *  @author Jesse Villarreal
 */

#include <csl_ccdc_aux.h>

#pragma CODE_SECTION (CSL_ccdcCheckSettings, ".text:csl_section:ccdc");

/** @brief	Checks for register setting violations
 *			If there are no violations, the function will return a CSL_SOK condition
 *			and the response value will be equal to 0.  If there are any violations, 
 *			the function will return the CSL_ESYS_FAIL error and the response value will
 *			have bits set which indicate any violations found.  The following are the 
 *			violation codes for the bits of the response variable:
 *			
 *			Bit 0: External WEN will not work when VP2SDR path is enabled
 *			Bit 1: In line alternating mode, the vertical start and number must be even
 *			Bit 2: At least one of the formatter initial addresses is beyond the max value
 *			Bit 3. The horizontal number for the video port is beyond the max value
 *			Bit 4. The vertical number for the video port is beyond the max value
 *			Bit 5: The video port needs to be enabled if the formatter is enabled
 *			Bit 6: In ycc input mode, the COLPTN should be set to 0s.
 *			Bit 7: In ycc input mode, the BLKCMP should be set to 0s.
 *			Bit 8: In ycc input mode, the fault pixel correction should be disabled.
 *			Bit 9: In ycc input mode, the Video port should be disabled.
 *			Bit10: In ycc input mode, the Formatter should be disabled.
 *			Bit11: In ycc input mode, the VP2SDR should be disabled.
 *			Bit12: In ycc input mode, the low pass filter should be disabled.
 *			Bit13: In ycc input mode, the ALAW should be disabled.
 *			Bit14: WARNING: In ycc input mode, neither the Resizer output or the SDRAM output is enabled.
 *			Bit15: In raw input mode, the resizer output path should not be enabled.
 *			16 - 31: RESERVED
*/
CSL_Status  CSL_ccdcCheckSettings(
    /** Pointer to the object that holds reference to the
     *  instance of CCDC requested after the call 
	 */
    CSL_CcdcHandle                         hCcdc,
    /** Pointer to structure holding the data
	 */
    CSL_CcdcErrorBits				   *response
	){

	CSL_CcdcErrorBits error = CSL_CCDC_ERR_NO_ERRORS;
	Uint16 fmten, horzVP, vertVP, vpen, vp2sdr, rsz, startLnV, numLnV;

	CSL_CcdcRegsOvly ccdcRegs =  hCcdc->regs;

	// READ ALL OF THE PERTINENT REGISTER FIELDS

	fmten =		CSL_FEXT(ccdcRegs->FMTCFG, CCDC_FMTCFG_FMTEN);
	horzVP =	CSL_FEXT(ccdcRegs->VP_OUT, CCDC_VP_OUT_HORZ_NUM);
	vertVP =	CSL_FEXT(ccdcRegs->VP_OUT, CCDC_VP_OUT_VERT_NUM);
	vpen =		CSL_FEXT(ccdcRegs->FMTCFG, CCDC_FMTCFG_VPEN);
	vp2sdr =	CSL_FEXT(ccdcRegs->SYN_MODE, CCDC_SYN_MODE_VP2SDR);
	rsz =		CSL_FEXT(ccdcRegs->SYN_MODE, CCDC_SYN_MODE_SDR2RSZ);
	startLnV =	CSL_FEXT(ccdcRegs->FMT_VERT, CCDC_FMT_VERT_FMTSLV);
	numLnV =	CSL_FEXT(ccdcRegs->FMT_VERT, CCDC_FMT_VERT_FMTLNV);


	//CHECK SETTINGS FOR VIOLATIONS

	{
		Uint8 exwen;

		exwen = CSL_FEXT(ccdcRegs->SYN_MODE, CCDC_SYN_MODE_EXWEN);

		if(exwen && vp2sdr)
			error |= CSL_CCDC_ERR_EXWEN_NOT_ALLOWED_WHEN_VP2SDR;
	}

	if(fmten)
	{
		Uint16 i, lnum, limit, lnalt, addr[8];

		lnalt =		CSL_FEXT(ccdcRegs->FMTCFG, CCDC_FMTCFG_LNALT);

		if(lnalt && ((startLnV%2) || (numLnV%2)))
			error |= CSL_CCDC_ERR_FMT_LNALT_VERT_NOT_EVEN;

		lnum = CSL_FEXT(ccdcRegs->FMTCFG, CCDC_FMTCFG_LNUM);

		addr[0] = CSL_FEXT(ccdcRegs->FMT_ADDR0, CCDC_FMT_ADDR0_INIT);
		addr[1] = CSL_FEXT(ccdcRegs->FMT_ADDR1, CCDC_FMT_ADDR1_INIT);
		addr[2] = CSL_FEXT(ccdcRegs->FMT_ADDR2, CCDC_FMT_ADDR2_INIT);
		addr[3] = CSL_FEXT(ccdcRegs->FMT_ADDR3, CCDC_FMT_ADDR3_INIT);
		addr[4] = CSL_FEXT(ccdcRegs->FMT_ADDR4, CCDC_FMT_ADDR4_INIT);
		addr[5] = CSL_FEXT(ccdcRegs->FMT_ADDR5, CCDC_FMT_ADDR5_INIT);
		addr[6] = CSL_FEXT(ccdcRegs->FMT_ADDR6, CCDC_FMT_ADDR6_INIT);
		addr[7] = CSL_FEXT(ccdcRegs->FMT_ADDR7, CCDC_FMT_ADDR7_INIT);
		
		switch(lnum)
		{
			case 0:	limit = 1376*4;	
					break;
			case 1: limit = 1376*2;	
					break;
			case 2:
			case 3: limit = 1376;	
					break;
			default :limit = 1376*4;;
		}

		for(i=0;i<8;i++)
			if(addr[i] > (limit-1))
				error |= CSL_CCDC_ERR_FMT_ADDR_INIT_OVER_MAX_VALUE;

		if(horzVP > limit)
			error |= CSL_CCDC_ERR_VP_HORZ_NUM_OVER_MAX_VALUE;

		if(vertVP > (numLnV-1)*(lnum+1))
			error |= CSL_CCDC_ERR_VP_VERT_NUM_OVER_MAX_VALUE;

		if(!vpen)
			error |= CSL_CCDC_ERR_VP_NOT_ENABLED;
	}

	if(horzVP > (1376*4))
		error |= CSL_CCDC_ERR_VP_HORZ_NUM_OVER_MAX_VALUE;

	if(vertVP > (numLnV-1))
		error |= CSL_CCDC_ERR_VP_VERT_NUM_OVER_MAX_VALUE;


	{
		Uint8 inputMode, rec656;

		inputMode = CSL_FEXT(ccdcRegs->SYN_MODE, CCDC_SYN_MODE_INPMOD);
		rec656 = CSL_FEXT(ccdcRegs->REC656IF, CCDC_REC656IF_R656ON);

		if(inputMode || rec656)
		{
			Uint8 fpc, lpf, alaw, wen;
			
			fpc = CSL_FEXT(ccdcRegs->FPC, CCDC_FPC_FPCEN);
			lpf = CSL_FEXT(ccdcRegs->SYN_MODE, CCDC_SYN_MODE_LPF);
			alaw = CSL_FEXT(ccdcRegs->ALAW, CCDC_ALAW_CCDTBL);
			wen = CSL_FEXT(ccdcRegs->SYN_MODE, CCDC_SYN_MODE_WEN);

			if(ccdcRegs->COLPTN)
				error |= CSL_CCDC_ERR_YCC_INPUT_COLPTN_SET;

			if(ccdcRegs->BLKCMP)
				error |= CSL_CCDC_ERR_YCC_INPUT_BLKCMP_SET;

			if(fpc)
				error |= CSL_CCDC_ERR_YCC_INPUT_FPC_SET;

			if(vpen)
				error |= CSL_CCDC_ERR_YCC_INPUT_VPEN_SET;

			if(fmten)
				error |= CSL_CCDC_ERR_YCC_INPUT_FMTEN_SET;

			if(vp2sdr)
				error |= CSL_CCDC_ERR_YCC_INPUT_VP2SDR_SET;

			if(lpf)
				error |= CSL_CCDC_ERR_YCC_INPUT_LPF_SET;

			if(alaw)
				error |= CSL_CCDC_ERR_YCC_INPUT_ALAW_SET;

			if(!(wen || rsz))
				error |= CSL_CCDC_ERR_YCC_INPUT_OUTPUT_NOT_SET_WARNING;
		}
		else
		{
			if(rsz)
				error |= CSL_CCDC_ERR_RAW_INPUT_RSZ_OUTPUT_SET;
		}
	}

	*response = error;

	if(error)
		return (CSL_ESYS_FAIL);
	else
		return (CSL_SOK);
}