cslr_ccdc_001.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_CCDC_FMT_ADDR3_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR3_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR3_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR3_RESETVAL      (0x00000000u)

/* FMT_ADDR4 */

#define CSL_CCDC_FMT_ADDR4_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR4_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR4_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR4_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR4_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR4_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR4_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR4_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR4_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR4_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR4_RESETVAL      (0x00000000u)

/* FMT_ADDR5 */

#define CSL_CCDC_FMT_ADDR5_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR5_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR5_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR5_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR5_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR5_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR5_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR5_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR5_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR5_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR5_RESETVAL      (0x00000000u)

/* FMT_ADDR6 */

#define CSL_CCDC_FMT_ADDR6_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR6_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR6_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR6_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR6_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR6_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR6_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR6_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR6_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR6_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR6_RESETVAL      (0x00000000u)

/* FMT_ADDR7 */

#define CSL_CCDC_FMT_ADDR7_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR7_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR7_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR7_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR7_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR7_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR7_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR7_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR7_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR7_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR7_RESETVAL      (0x00000000u)

/* PRGEVEN_0 */

#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_MASK (0xE0000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_SHIFT (0x0000001Du)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_RESETVAL (0x00000000u)

/*----EVEN7_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN7_UPDT_MASK (0x10000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_UPDT_SHIFT (0x0000001Cu)
#define CSL_CCDC_PRGEVEN_0_EVEN7_UPDT_RESETVAL (0x00000000u)

/*----EVEN7_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN7_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN7_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_MASK (0x0E000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_SHIFT (0x00000019u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_RESETVAL (0x00000000u)

/*----EVEN6_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN6_UPDT_MASK (0x01000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_UPDT_SHIFT (0x00000018u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_UPDT_RESETVAL (0x00000000u)

/*----EVEN6_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN6_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN6_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_MASK (0x00E00000u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_SHIFT (0x00000015u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_RESETVAL (0x00000000u)

/*----EVEN5_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN5_UPDT_MASK (0x00100000u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_UPDT_SHIFT (0x00000014u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_UPDT_RESETVAL (0x00000000u)

/*----EVEN5_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN5_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN5_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_MASK (0x000E0000u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_SHIFT (0x00000011u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_RESETVAL (0x00000000u)

/*----EVEN4_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN4_UPDT_MASK (0x00010000u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_UPDT_SHIFT (0x00000010u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_UPDT_RESETVAL (0x00000000u)

/*----EVEN4_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN4_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN4_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_MASK (0x0000E000u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_SHIFT (0x0000000Du)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_RESETVAL (0x00000000u)

/*----EVEN3_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN3_UPDT_MASK (0x00001000u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_UPDT_SHIFT (0x0000000Cu)
#define CSL_CCDC_PRGEVEN_0_EVEN3_UPDT_RESETVAL (0x00000000u)

/*----EVEN3_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN3_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN3_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_MASK (0x00000E00u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_SHIFT (0x00000009u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_RESETVAL (0x00000000u)

/*----EVEN2_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN2_UPDT_MASK (0x00000100u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_UPDT_SHIFT (0x00000008u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_UPDT_RESETVAL (0x00000000u)

/*----EVEN2_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN2_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN2_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_MASK (0x000000E0u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_SHIFT (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_RESETVAL (0x00000000u)

/*----EVEN1_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN1_UPDT_MASK (0x00000010u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_UPDT_SHIFT (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_UPDT_RESETVAL (0x00000000u)

/*----EVEN1_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN1_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN1_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_MASK (0x0000000Eu)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_SHIFT (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_RESETVAL (0x00000000u)

/*----EVEN0_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_0_EVEN0_UPDT_MASK (0x00000001u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_UPDT_SHIFT (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_UPDT_RESETVAL (0x00000000u)

/*----EVEN0_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_0_EVEN0_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_0_EVEN0_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_0_RESETVAL      (0x00000000u)

/* PRGEVEN_1 */

#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_MASK (0xE0000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_SHIFT (0x0000001Du)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_RESETVAL (0x00000000u)

/*----EVEN15_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_1_EVEN15_UPDT_MASK (0x10000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_UPDT_SHIFT (0x0000001Cu)
#define CSL_CCDC_PRGEVEN_1_EVEN15_UPDT_RESETVAL (0x00000000u)

/*----EVEN15_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_1_EVEN15_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN15_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_MASK (0x0E000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_SHIFT (0x00000019u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_RESETVAL (0x00000000u)

/*----EVEN14_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_1_EVEN14_UPDT_MASK (0x01000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_UPDT_SHIFT (0x00000018u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_UPDT_RESETVAL (0x00000000u)

/*----EVEN14_UPDT Tokens----*/
#define CSL_CCDC_PRGEVEN_1_EVEN14_UPDT_INCR (0x00000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN14_UPDT_DECR (0x00000001u)

#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_MASK (0x00E00000u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_SHIFT (0x00000015u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_RESETVAL (0x00000000u)

/*----EVEN13_ADDR Tokens----*/
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR0 (0x00000000u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR1 (0x00000001u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR2 (0x00000002u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR3 (0x00000003u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR4 (0x00000004u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR5 (0x00000005u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR6 (0x00000006u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_ADDR_ADDR7 (0x00000007u)

#define CSL_CCDC_PRGEVEN_1_EVEN13_UPDT_MASK (0x00100000u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_UPDT_SHIFT (0x00000014u)
#define CSL_CCDC_PRGEVEN_1_EVEN13_UPDT_RESETVAL (0x00000000u)