cslr_ccdc_001.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_CCDC_BLKCMP_B_MG_RESETVAL    (0x00000000u)

#define CSL_CCDC_BLKCMP_RESETVAL         (0x00000000u)

/* FPC */

#define CSL_CCDC_FPC_FPERR_MASK          (0x00010000u)
#define CSL_CCDC_FPC_FPERR_SHIFT         (0x00000010u)
#define CSL_CCDC_FPC_FPERR_RESETVAL      (0x00000000u)

/*----FPERR Tokens----*/
#define CSL_CCDC_FPC_FPERR_NOERROR       (0x00000000u)
#define CSL_CCDC_FPC_FPERR_ERROR         (0x00000001u)

#define CSL_CCDC_FPC_FPCEN_MASK          (0x00008000u)
#define CSL_CCDC_FPC_FPCEN_SHIFT         (0x0000000Fu)
#define CSL_CCDC_FPC_FPCEN_RESETVAL      (0x00000000u)

/*----FPCEN Tokens----*/
#define CSL_CCDC_FPC_FPCEN_DISABLED      (0x00000000u)
#define CSL_CCDC_FPC_FPCEN_ENABLED       (0x00000001u)

#define CSL_CCDC_FPC_FPNUM_MASK          (0x00007FFFu)
#define CSL_CCDC_FPC_FPNUM_SHIFT         (0x00000000u)
#define CSL_CCDC_FPC_FPNUM_RESETVAL      (0x00000000u)

#define CSL_CCDC_FPC_RESETVAL            (0x00000000u)

/* FPC_ADDR */

#define CSL_CCDC_FPC_ADDR_FPC_ADDR_MASK  (0xFFFFFFFFu)
#define CSL_CCDC_FPC_ADDR_FPC_ADDR_SHIFT (0x00000000u)
#define CSL_CCDC_FPC_ADDR_FPC_ADDR_RESETVAL (0x00000000u)

#define CSL_CCDC_FPC_ADDR_RESETVAL       (0x00000000u)

/* VDINT */

#define CSL_CCDC_VDINT_VDINT0_MASK       (0x7FFF0000u)
#define CSL_CCDC_VDINT_VDINT0_SHIFT      (0x00000010u)
#define CSL_CCDC_VDINT_VDINT0_RESETVAL   (0x00000000u)

#define CSL_CCDC_VDINT_VDINT1_MASK       (0x00007FFFu)
#define CSL_CCDC_VDINT_VDINT1_SHIFT      (0x00000000u)
#define CSL_CCDC_VDINT_VDINT1_RESETVAL   (0x00000000u)

#define CSL_CCDC_VDINT_RESETVAL          (0x00000000u)

/* ALAW */

#define CSL_CCDC_ALAW_CCDTBL_MASK        (0x00000008u)
#define CSL_CCDC_ALAW_CCDTBL_SHIFT       (0x00000003u)
#define CSL_CCDC_ALAW_CCDTBL_RESETVAL    (0x00000000u)

/*----CCDTBL Tokens----*/
#define CSL_CCDC_ALAW_CCDTBL_DISABLE     (0x00000000u)
#define CSL_CCDC_ALAW_CCDTBL_ENABLE      (0x00000001u)

#define CSL_CCDC_ALAW_GWDI_MASK          (0x00000007u)
#define CSL_CCDC_ALAW_GWDI_SHIFT         (0x00000000u)
#define CSL_CCDC_ALAW_GWDI_RESETVAL      (0x00000004u)

/*----GWDI Tokens----*/
#define CSL_CCDC_ALAW_GWDI_BITS_15_6     (0x00000000u)
#define CSL_CCDC_ALAW_GWDI_BITS_14_5     (0x00000001u)
#define CSL_CCDC_ALAW_GWDI_BITS_13_4     (0x00000002u)
#define CSL_CCDC_ALAW_GWDI_BITS_12_3     (0x00000003u)
#define CSL_CCDC_ALAW_GWDI_BITS_11_2     (0x00000004u)
#define CSL_CCDC_ALAW_GWDI_BITS_10_1     (0x00000005u)
#define CSL_CCDC_ALAW_GWDI_BITS_09_0     (0x00000006u)

#define CSL_CCDC_ALAW_RESETVAL           (0x00000004u)

/* REC656IF */

#define CSL_CCDC_REC656IF_ECCFVH_MASK    (0x00000002u)
#define CSL_CCDC_REC656IF_ECCFVH_SHIFT   (0x00000001u)
#define CSL_CCDC_REC656IF_ECCFVH_RESETVAL (0x00000000u)

/*----ECCFVH Tokens----*/
#define CSL_CCDC_REC656IF_ECCFVH_DISABLE (0x00000000u)
#define CSL_CCDC_REC656IF_ECCFVH_ENABLE  (0x00000001u)

#define CSL_CCDC_REC656IF_R656ON_MASK    (0x00000001u)
#define CSL_CCDC_REC656IF_R656ON_SHIFT   (0x00000000u)
#define CSL_CCDC_REC656IF_R656ON_RESETVAL (0x00000000u)

/*----R656ON Tokens----*/
#define CSL_CCDC_REC656IF_R656ON_DISABLE (0x00000000u)
#define CSL_CCDC_REC656IF_R656ON_ENABLE  (0x00000001u)

#define CSL_CCDC_REC656IF_RESETVAL       (0x00000000u)

/* CCDCFG */

#define CSL_CCDC_CCDCFG_VDLC_MASK        (0x00008000u)
#define CSL_CCDC_CCDCFG_VDLC_SHIFT       (0x0000000Fu)
#define CSL_CCDC_CCDCFG_VDLC_RESETVAL    (0x00000000u)

/*----VDLC Tokens----*/
#define CSL_CCDC_CCDCFG_VDLC_LATCHEDONVSYNC (0x00000000u)
#define CSL_CCDC_CCDCFG_VDLC_NOTLATCHEDONVSYNC (0x00000001u)

#define CSL_CCDC_CCDCFG_MSBINVI_MASK     (0x00002000u)
#define CSL_CCDC_CCDCFG_MSBINVI_SHIFT    (0x0000000Du)
#define CSL_CCDC_CCDCFG_MSBINVI_RESETVAL (0x00000000u)

/*----MSBINVI Tokens----*/
#define CSL_CCDC_CCDCFG_MSBINVI_NORMAL   (0x00000000u)
#define CSL_CCDC_CCDCFG_MSBINVI_MSBINVERTED (0x00000001u)

#define CSL_CCDC_CCDCFG_BSWD_MASK        (0x00001000u)
#define CSL_CCDC_CCDCFG_BSWD_SHIFT       (0x0000000Cu)
#define CSL_CCDC_CCDCFG_BSWD_RESETVAL    (0x00000000u)

/*----BSWD Tokens----*/
#define CSL_CCDC_CCDCFG_BSWD_NORMAL      (0x00000000u)
#define CSL_CCDC_CCDCFG_BSWD_SWAPBYTES   (0x00000001u)

#define CSL_CCDC_CCDCFG_Y8POS_MASK       (0x00000800u)
#define CSL_CCDC_CCDCFG_Y8POS_SHIFT      (0x0000000Bu)
#define CSL_CCDC_CCDCFG_Y8POS_RESETVAL   (0x00000000u)

/*----Y8POS Tokens----*/
#define CSL_CCDC_CCDCFG_Y8POS_EVENPIXEL  (0x00000000u)
#define CSL_CCDC_CCDCFG_Y8POS_ODDPIXEL   (0x00000001u)

#define CSL_CCDC_CCDCFG_WENLOG_MASK      (0x00000100u)
#define CSL_CCDC_CCDCFG_WENLOG_SHIFT     (0x00000008u)
#define CSL_CCDC_CCDCFG_WENLOG_RESETVAL  (0x00000000u)

/*----WENLOG Tokens----*/
#define CSL_CCDC_CCDCFG_WENLOG_AND       (0x00000000u)
#define CSL_CCDC_CCDCFG_WENLOG_OR        (0x00000001u)

#define CSL_CCDC_CCDCFG_FIDMD_MASK       (0x000000C0u)
#define CSL_CCDC_CCDCFG_FIDMD_SHIFT      (0x00000006u)
#define CSL_CCDC_CCDCFG_FIDMD_RESETVAL   (0x00000000u)

/*----FIDMD Tokens----*/
#define CSL_CCDC_CCDCFG_FIDMD_LATCH_AT_VSYNC (0x00000000u)
#define CSL_CCDC_CCDCFG_FIDMD_NO_LATCH   (0x00000001u)
#define CSL_CCDC_CCDCFG_FIDMD_LATCH_AT_VD_EDGE (0x00000002u)
#define CSL_CCDC_CCDCFG_FIDMD_LATCH_ON_VD_HD_PHASE (0x00000003u)

#define CSL_CCDC_CCDCFG_BW656_MASK       (0x00000020u)
#define CSL_CCDC_CCDCFG_BW656_SHIFT      (0x00000005u)
#define CSL_CCDC_CCDCFG_BW656_RESETVAL   (0x00000000u)

/*----BW656 Tokens----*/
#define CSL_CCDC_CCDCFG_BW656__8_BITS    (0x00000000u)
#define CSL_CCDC_CCDCFG_BW656__10_BITS   (0x00000001u)

#define CSL_CCDC_CCDCFG_YCINSWP_MASK     (0x00000010u)
#define CSL_CCDC_CCDCFG_YCINSWP_SHIFT    (0x00000004u)
#define CSL_CCDC_CCDCFG_YCINSWP_RESETVAL (0x00000000u)

/*----YCINSWP Tokens----*/
#define CSL_CCDC_CCDCFG_YCINSWP_NO_YCIN_SWAP (0x00000000u)
#define CSL_CCDC_CCDCFG_YCINSWP_YCIN_SWAP (0x00000001u)

#define CSL_CCDC_CCDCFG_RESETVAL         (0x00000000u)

/* FMTCFG */

#define CSL_CCDC_FMTCFG_VPIF_FRQ_MASK    (0x00070000u)
#define CSL_CCDC_FMTCFG_VPIF_FRQ_SHIFT   (0x00000010u)
#define CSL_CCDC_FMTCFG_VPIF_FRQ_RESETVAL (0x00000000u)

/*----VPIF_FRQ Tokens----*/
#define CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_HALF (0x00000000u)
#define CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_THIRDHALF (0x00000001u)
#define CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_FOURTHHALF (0x00000002u)
#define CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_FIFTHHALF (0x00000003u)
#define CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_SIXTHHALF (0x00000004u)

#define CSL_CCDC_FMTCFG_VPEN_MASK        (0x00008000u)
#define CSL_CCDC_FMTCFG_VPEN_SHIFT       (0x0000000Fu)
#define CSL_CCDC_FMTCFG_VPEN_RESETVAL    (0x00000000u)

/*----VPEN Tokens----*/
#define CSL_CCDC_FMTCFG_VPEN_DISABLE     (0x00000000u)
#define CSL_CCDC_FMTCFG_VPEN_ENABLE      (0x00000001u)

#define CSL_CCDC_FMTCFG_VPIN_MASK        (0x00007000u)
#define CSL_CCDC_FMTCFG_VPIN_SHIFT       (0x0000000Cu)
#define CSL_CCDC_FMTCFG_VPIN_RESETVAL    (0x00000004u)

/*----VPIN Tokens----*/
#define CSL_CCDC_FMTCFG_VPIN_BITS_15_06  (0x00000000u)
#define CSL_CCDC_FMTCFG_VPIN_BITS_14_05  (0x00000001u)
#define CSL_CCDC_FMTCFG_VPIN_BITS_13_04  (0x00000002u)
#define CSL_CCDC_FMTCFG_VPIN_BITS_12_03  (0x00000003u)
#define CSL_CCDC_FMTCFG_VPIN_BITS_11_02  (0x00000004u)
#define CSL_CCDC_FMTCFG_VPIN_BITS_10_01  (0x00000005u)
#define CSL_CCDC_FMTCFG_VPIN_BITS_09_00  (0x00000006u)

#define CSL_CCDC_FMTCFG_PLEN_EVEN_MASK   (0x00000F00u)
#define CSL_CCDC_FMTCFG_PLEN_EVEN_SHIFT  (0x00000008u)
#define CSL_CCDC_FMTCFG_PLEN_EVEN_RESETVAL (0x00000000u)

#define CSL_CCDC_FMTCFG_PLEN_ODD_MASK    (0x000000F0u)
#define CSL_CCDC_FMTCFG_PLEN_ODD_SHIFT   (0x00000004u)
#define CSL_CCDC_FMTCFG_PLEN_ODD_RESETVAL (0x00000000u)

#define CSL_CCDC_FMTCFG_LNUM_MASK        (0x0000000Cu)
#define CSL_CCDC_FMTCFG_LNUM_SHIFT       (0x00000002u)
#define CSL_CCDC_FMTCFG_LNUM_RESETVAL    (0x00000000u)

/*----LNUM Tokens----*/
#define CSL_CCDC_FMTCFG_LNUM__1LINE      (0x00000000u)
#define CSL_CCDC_FMTCFG_LNUM__2LINES     (0x00000001u)
#define CSL_CCDC_FMTCFG_LNUM__3LINES     (0x00000002u)
#define CSL_CCDC_FMTCFG_LNUM__4LINES     (0x00000003u)

#define CSL_CCDC_FMTCFG_LNALT_MASK       (0x00000002u)
#define CSL_CCDC_FMTCFG_LNALT_SHIFT      (0x00000001u)
#define CSL_CCDC_FMTCFG_LNALT_RESETVAL   (0x00000000u)

/*----LNALT Tokens----*/
#define CSL_CCDC_FMTCFG_LNALT_NORMALMODE (0x00000000u)
#define CSL_CCDC_FMTCFG_LNALT_LINEALTERNATINGMODE (0x00000001u)

#define CSL_CCDC_FMTCFG_FMTEN_MASK       (0x00000001u)
#define CSL_CCDC_FMTCFG_FMTEN_SHIFT      (0x00000000u)
#define CSL_CCDC_FMTCFG_FMTEN_RESETVAL   (0x00000000u)

/*----FMTEN Tokens----*/
#define CSL_CCDC_FMTCFG_FMTEN_OFF        (0x00000000u)
#define CSL_CCDC_FMTCFG_FMTEN_ON         (0x00000001u)

#define CSL_CCDC_FMTCFG_RESETVAL         (0x00004000u)

/* FMT_HORZ */

#define CSL_CCDC_FMT_HORZ_FMTSPH_MASK    (0x1FFF0000u)
#define CSL_CCDC_FMT_HORZ_FMTSPH_SHIFT   (0x00000010u)
#define CSL_CCDC_FMT_HORZ_FMTSPH_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_HORZ_FMTLNH_MASK    (0x00001FFFu)
#define CSL_CCDC_FMT_HORZ_FMTLNH_SHIFT   (0x00000000u)
#define CSL_CCDC_FMT_HORZ_FMTLNH_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_HORZ_RESETVAL       (0x00000000u)

/* FMT_VERT */

#define CSL_CCDC_FMT_VERT_FMTSLV_MASK    (0x1FFF0000u)
#define CSL_CCDC_FMT_VERT_FMTSLV_SHIFT   (0x00000010u)
#define CSL_CCDC_FMT_VERT_FMTSLV_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_VERT_FMTLNV_MASK    (0x00001FFFu)
#define CSL_CCDC_FMT_VERT_FMTLNV_SHIFT   (0x00000000u)
#define CSL_CCDC_FMT_VERT_FMTLNV_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_VERT_RESETVAL       (0x00000000u)

/* FMT_ADDR0 */

#define CSL_CCDC_FMT_ADDR0_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR0_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR0_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR0_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR0_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR0_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR0_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR0_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR0_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR0_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR0_RESETVAL      (0x00000000u)

/* FMT_ADDR1 */

#define CSL_CCDC_FMT_ADDR1_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR1_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR1_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR1_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR1_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR1_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR1_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR1_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR1_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR1_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR1_RESETVAL      (0x00000000u)

/* FMT_ADDR2 */

#define CSL_CCDC_FMT_ADDR2_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR2_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR2_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR2_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR2_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR2_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR2_LINE__4THLINE (0x00000003u)

#define CSL_CCDC_FMT_ADDR2_INIT_MASK     (0x00001FFFu)
#define CSL_CCDC_FMT_ADDR2_INIT_SHIFT    (0x00000000u)
#define CSL_CCDC_FMT_ADDR2_INIT_RESETVAL (0x00000000u)

#define CSL_CCDC_FMT_ADDR2_RESETVAL      (0x00000000u)

/* FMT_ADDR3 */

#define CSL_CCDC_FMT_ADDR3_LINE_MASK     (0x03000000u)
#define CSL_CCDC_FMT_ADDR3_LINE_SHIFT    (0x00000018u)
#define CSL_CCDC_FMT_ADDR3_LINE_RESETVAL (0x00000000u)

/*----LINE Tokens----*/
#define CSL_CCDC_FMT_ADDR3_LINE__1STLINE (0x00000000u)
#define CSL_CCDC_FMT_ADDR3_LINE__2NDLINE (0x00000001u)
#define CSL_CCDC_FMT_ADDR3_LINE__3RDLINE (0x00000002u)
#define CSL_CCDC_FMT_ADDR3_LINE__4THLINE (0x00000003u)