cslr_resz_001.h

TI达芬奇dm644x各硬件模块测试代码

#ifndef _CSLR_RESZ_1_H_
#define _CSLR_RESZ_1_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_resz_1.h
 * 
 * \brief This file contains the Register Desciptions for RESZ
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 PCR;
    volatile Uint32 RSZ_CNT;
    volatile Uint32 OUT_SIZE;
    volatile Uint32 IN_START;
    volatile Uint32 IN_SIZE;
    volatile Uint32 SDR_INADD;
    volatile Uint32 SDR_INOFF;
    volatile Uint32 SDR_OUTADD;
    volatile Uint32 SDR_OUTOFF;
    volatile Uint32 HFILT10;
    volatile Uint32 HFILT32;
    volatile Uint32 HFILT54;
    volatile Uint32 HFILT76;
    volatile Uint32 HFILT98;
    volatile Uint32 HFILT1110;
    volatile Uint32 HFILT1312;
    volatile Uint32 HFILT1514;
    volatile Uint32 HFILT1716;
    volatile Uint32 HFILT1918;
    volatile Uint32 HFILT2120;
    volatile Uint32 HFILT2322;
    volatile Uint32 HFILT2524;
    volatile Uint32 HFILT2726;
    volatile Uint32 HFILT2928;
    volatile Uint32 HFILT3130;
    volatile Uint32 VFILT10;
    volatile Uint32 VFILT32;
    volatile Uint32 VFILT54;
    volatile Uint32 VFILT76;
    volatile Uint32 VFILT98;
    volatile Uint32 VFILT1110;
    volatile Uint32 VFILT1312;
    volatile Uint32 VFILT1514;
    volatile Uint32 VFILT1716;
    volatile Uint32 VFILT1918;
    volatile Uint32 VFILT2120;
    volatile Uint32 VFILT2322;
    volatile Uint32 VFILT2524;
    volatile Uint32 VFILT2726;
    volatile Uint32 VFILT2928;
    volatile Uint32 VFILT3130;
    volatile Uint32 YENH;
} CSL_ReszRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID */

#define CSL_RESZ_PID_TID_MASK            (0x00FF0000u)
#define CSL_RESZ_PID_TID_SHIFT           (0x00000010u)
#define CSL_RESZ_PID_TID_RESETVAL        (0x00000010u)

#define CSL_RESZ_PID_CID_MASK            (0x0000FF00u)
#define CSL_RESZ_PID_CID_SHIFT           (0x00000008u)
#define CSL_RESZ_PID_CID_RESETVAL        (0x000000FEu)

#define CSL_RESZ_PID_PREV_MASK           (0x000000FFu)
#define CSL_RESZ_PID_PREV_SHIFT          (0x00000000u)
#define CSL_RESZ_PID_PREV_RESETVAL       (0x00000000u)

#define CSL_RESZ_PID_RESETVAL            (0x0010FE00u)

/* PCR */

#define CSL_RESZ_PCR_BUSY_MASK           (0x00000002u)
#define CSL_RESZ_PCR_BUSY_SHIFT          (0x00000001u)
#define CSL_RESZ_PCR_BUSY_RESETVAL       (0x00000000u)

/*----BUSY Tokens----*/
#define CSL_RESZ_PCR_BUSY_NOTBUSY        (0x00000000u)
#define CSL_RESZ_PCR_BUSY_BUSY           (0x00000001u)

#define CSL_RESZ_PCR_ENABLE_MASK         (0x00000001u)
#define CSL_RESZ_PCR_ENABLE_SHIFT        (0x00000000u)
#define CSL_RESZ_PCR_ENABLE_RESETVAL     (0x00000000u)

/*----ENABLE Tokens----*/
#define CSL_RESZ_PCR_ENABLE_DISABLE      (0x00000000u)
#define CSL_RESZ_PCR_ENABLE_ENABLE       (0x00000001u)

#define CSL_RESZ_PCR_RESETVAL            (0x00000000u)

/* RSZ_CNT */

#define CSL_RESZ_RSZ_CNT_CBILIN_MASK     (0x20000000u)
#define CSL_RESZ_RSZ_CNT_CBILIN_SHIFT    (0x0000001Du)
#define CSL_RESZ_RSZ_CNT_CBILIN_RESETVAL (0x00000000u)

/*----CBILIN Tokens----*/
#define CSL_RESZ_RSZ_CNT_CBILIN_SAME_AS_LUMA (0x00000000u)
#define CSL_RESZ_RSZ_CNT_CBILIN_BILIN_INTERP (0x00000001u)

#define CSL_RESZ_RSZ_CNT_INPSRC_MASK     (0x10000000u)
#define CSL_RESZ_RSZ_CNT_INPSRC_SHIFT    (0x0000001Cu)
#define CSL_RESZ_RSZ_CNT_INPSRC_RESETVAL (0x00000000u)

/*----INPSRC Tokens----*/
#define CSL_RESZ_RSZ_CNT_INPSRC_PREVIEW_OR_CCDC (0x00000000u)
#define CSL_RESZ_RSZ_CNT_INPSRC_SDRAM    (0x00000001u)

#define CSL_RESZ_RSZ_CNT_INPTYP_MASK     (0x08000000u)
#define CSL_RESZ_RSZ_CNT_INPTYP_SHIFT    (0x0000001Bu)
#define CSL_RESZ_RSZ_CNT_INPTYP_RESETVAL (0x00000000u)

/*----INPTYP Tokens----*/
#define CSL_RESZ_RSZ_CNT_INPTYP_YUV422_INTERLEAVED (0x00000000u)
#define CSL_RESZ_RSZ_CNT_INPTYP_COLOR_SEP_8BIT (0x00000001u)

#define CSL_RESZ_RSZ_CNT_YCPOS_MASK      (0x04000000u)
#define CSL_RESZ_RSZ_CNT_YCPOS_SHIFT     (0x0000001Au)
#define CSL_RESZ_RSZ_CNT_YCPOS_RESETVAL  (0x00000000u)

/*----YCPOS Tokens----*/
#define CSL_RESZ_RSZ_CNT_YCPOS_YC        (0x00000000u)
#define CSL_RESZ_RSZ_CNT_YCPOS_CY        (0x00000001u)

#define CSL_RESZ_RSZ_CNT_VSTPH_MASK      (0x03800000u)
#define CSL_RESZ_RSZ_CNT_VSTPH_SHIFT     (0x00000017u)
#define CSL_RESZ_RSZ_CNT_VSTPH_RESETVAL  (0x00000000u)

#define CSL_RESZ_RSZ_CNT_HSTPH_MASK      (0x00700000u)
#define CSL_RESZ_RSZ_CNT_HSTPH_SHIFT     (0x00000014u)
#define CSL_RESZ_RSZ_CNT_HSTPH_RESETVAL  (0x00000000u)

#define CSL_RESZ_RSZ_CNT_VRSZ_MASK       (0x000FFC00u)
#define CSL_RESZ_RSZ_CNT_VRSZ_SHIFT      (0x0000000Au)
#define CSL_RESZ_RSZ_CNT_VRSZ_RESETVAL   (0x000000FFu)

#define CSL_RESZ_RSZ_CNT_HRSZ_MASK       (0x000003FFu)
#define CSL_RESZ_RSZ_CNT_HRSZ_SHIFT      (0x00000000u)
#define CSL_RESZ_RSZ_CNT_HRSZ_RESETVAL   (0x000000FFu)

#define CSL_RESZ_RSZ_CNT_RESETVAL        (0x0003FCFFu)

/* OUT_SIZE */

#define CSL_RESZ_OUT_SIZE_VERT_MASK      (0x07FF0000u)
#define CSL_RESZ_OUT_SIZE_VERT_SHIFT     (0x00000010u)
#define CSL_RESZ_OUT_SIZE_VERT_RESETVAL  (0x00000000u)

#define CSL_RESZ_OUT_SIZE_HORZ_MASK      (0x000007FFu)
#define CSL_RESZ_OUT_SIZE_HORZ_SHIFT     (0x00000000u)
#define CSL_RESZ_OUT_SIZE_HORZ_RESETVAL  (0x00000000u)

#define CSL_RESZ_OUT_SIZE_RESETVAL       (0x00000000u)

/* IN_START */

#define CSL_RESZ_IN_START_VERT_ST_MASK   (0x1FFF0000u)
#define CSL_RESZ_IN_START_VERT_ST_SHIFT  (0x00000010u)
#define CSL_RESZ_IN_START_VERT_ST_RESETVAL (0x00000000u)

#define CSL_RESZ_IN_START_HORZ_ST_MASK   (0x00001FFFu)
#define CSL_RESZ_IN_START_HORZ_ST_SHIFT  (0x00000000u)
#define CSL_RESZ_IN_START_HORZ_ST_RESETVAL (0x00000000u)

#define CSL_RESZ_IN_START_RESETVAL       (0x00000000u)

/* IN_SIZE */

#define CSL_RESZ_IN_SIZE_VERT_MASK       (0x1FFF0000u)
#define CSL_RESZ_IN_SIZE_VERT_SHIFT      (0x00000010u)
#define CSL_RESZ_IN_SIZE_VERT_RESETVAL   (0x00000000u)

#define CSL_RESZ_IN_SIZE_HORZ_MASK       (0x00001FFFu)
#define CSL_RESZ_IN_SIZE_HORZ_SHIFT      (0x00000000u)
#define CSL_RESZ_IN_SIZE_HORZ_RESETVAL   (0x00000000u)

#define CSL_RESZ_IN_SIZE_RESETVAL        (0x00000000u)

/* SDR_INADD */

#define CSL_RESZ_SDR_INADD_SDR_INADD_MASK (0xFFFFFFFFu)
#define CSL_RESZ_SDR_INADD_SDR_INADD_SHIFT (0x00000000u)
#define CSL_RESZ_SDR_INADD_SDR_INADD_RESETVAL (0x00000000u)

#define CSL_RESZ_SDR_INADD_RESETVAL      (0x00000000u)

/* SDR_INOFF */

#define CSL_RESZ_SDR_INOFF_OFFSET_MASK   (0x0000FFFFu)
#define CSL_RESZ_SDR_INOFF_OFFSET_SHIFT  (0x00000000u)
#define CSL_RESZ_SDR_INOFF_OFFSET_RESETVAL (0x00000000u)

#define CSL_RESZ_SDR_INOFF_RESETVAL      (0x00000000u)

/* SDR_OUTADD */

#define CSL_RESZ_SDR_OUTADD_SDR_OUTADD_MASK (0xFFFFFFFFu)
#define CSL_RESZ_SDR_OUTADD_SDR_OUTADD_SHIFT (0x00000000u)
#define CSL_RESZ_SDR_OUTADD_SDR_OUTADD_RESETVAL (0x00000000u)

#define CSL_RESZ_SDR_OUTADD_RESETVAL     (0x00000000u)

/* SDR_OUTOFF */

#define CSL_RESZ_SDR_OUTOFF_OFFSET_MASK  (0x0000FFFFu)
#define CSL_RESZ_SDR_OUTOFF_OFFSET_SHIFT (0x00000000u)
#define CSL_RESZ_SDR_OUTOFF_OFFSET_RESETVAL (0x00000000u)

#define CSL_RESZ_SDR_OUTOFF_RESETVAL     (0x00000000u)

/* HFILT10 */

#define CSL_RESZ_HFILT10_COEF1_MASK      (0x03FF0000u)
#define CSL_RESZ_HFILT10_COEF1_SHIFT     (0x00000010u)
#define CSL_RESZ_HFILT10_COEF1_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT10_COEF0_MASK      (0x000003FFu)
#define CSL_RESZ_HFILT10_COEF0_SHIFT     (0x00000000u)
#define CSL_RESZ_HFILT10_COEF0_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT10_RESETVAL        (0x00000000u)

/* HFILT32 */

#define CSL_RESZ_HFILT32_COEF3_MASK      (0x03FF0000u)
#define CSL_RESZ_HFILT32_COEF3_SHIFT     (0x00000010u)
#define CSL_RESZ_HFILT32_COEF3_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT32_COEF2_MASK      (0x000003FFu)
#define CSL_RESZ_HFILT32_COEF2_SHIFT     (0x00000000u)
#define CSL_RESZ_HFILT32_COEF2_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT32_RESETVAL        (0x00000000u)

/* HFILT54 */

#define CSL_RESZ_HFILT54_COEF5_MASK      (0x03FF0000u)
#define CSL_RESZ_HFILT54_COEF5_SHIFT     (0x00000010u)
#define CSL_RESZ_HFILT54_COEF5_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT54_COEF4_MASK      (0x000003FFu)
#define CSL_RESZ_HFILT54_COEF4_SHIFT     (0x00000000u)
#define CSL_RESZ_HFILT54_COEF4_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT54_RESETVAL        (0x00000000u)

/* HFILT76 */

#define CSL_RESZ_HFILT76_COEF7_MASK      (0x03FF0000u)
#define CSL_RESZ_HFILT76_COEF7_SHIFT     (0x00000010u)
#define CSL_RESZ_HFILT76_COEF7_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT76_COEF6_MASK      (0x000003FFu)
#define CSL_RESZ_HFILT76_COEF6_SHIFT     (0x00000000u)
#define CSL_RESZ_HFILT76_COEF6_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT76_RESETVAL        (0x00000000u)

/* HFILT98 */

#define CSL_RESZ_HFILT98_COEF9_MASK      (0x03FF0000u)
#define CSL_RESZ_HFILT98_COEF9_SHIFT     (0x00000010u)
#define CSL_RESZ_HFILT98_COEF9_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT98_COEF8_MASK      (0x000003FFu)
#define CSL_RESZ_HFILT98_COEF8_SHIFT     (0x00000000u)
#define CSL_RESZ_HFILT98_COEF8_RESETVAL  (0x00000000u)

#define CSL_RESZ_HFILT98_RESETVAL        (0x00000000u)

/* HFILT1110 */

#define CSL_RESZ_HFILT1110_COEF11_MASK   (0x03FF0000u)
#define CSL_RESZ_HFILT1110_COEF11_SHIFT  (0x00000010u)
#define CSL_RESZ_HFILT1110_COEF11_RESETVAL (0x00000000u)

#define CSL_RESZ_HFILT1110_COEF10_MASK   (0x000003FFu)
#define CSL_RESZ_HFILT1110_COEF10_SHIFT  (0x00000000u)
#define CSL_RESZ_HFILT1110_COEF10_RESETVAL (0x00000000u)

#define CSL_RESZ_HFILT1110_RESETVAL      (0x00000000u)

/* HFILT1312 */

#define CSL_RESZ_HFILT1312_COEF13_MASK   (0x03FF0000u)
#define CSL_RESZ_HFILT1312_COEF13_SHIFT  (0x00000010u)
#define CSL_RESZ_HFILT1312_COEF13_RESETVAL (0x00000000u)

#define CSL_RESZ_HFILT1312_COEF12_MASK   (0x000003FFu)
#define CSL_RESZ_HFILT1312_COEF12_SHIFT  (0x00000000u)
#define CSL_RESZ_HFILT1312_COEF12_RESETVAL (0x00000000u)

#define CSL_RESZ_HFILT1312_RESETVAL      (0x00000000u)

/* HFILT1514 */

#define CSL_RESZ_HFILT1514_COEF15_MASK   (0x03FF0000u)
#define CSL_RESZ_HFILT1514_COEF15_SHIFT  (0x00000010u)
#define CSL_RESZ_HFILT1514_COEF15_RESETVAL (0x00000000u)

#define CSL_RESZ_HFILT1514_COEF14_MASK   (0x000003FFu)
#define CSL_RESZ_HFILT1514_COEF14_SHIFT  (0x00000000u)
#define CSL_RESZ_HFILT1514_COEF14_RESETVAL (0x00000000u)