cslr_vpss_001.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_VPSS_GLB_REG_2_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_2_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_2_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_2_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_2_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_2_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_2_RESETVAL      (0x00000000u)

/* GLB_REG_3 */

#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_3_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_3_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_3_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_3_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_3_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_3_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_3_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_3_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_3_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_3_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_3_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_3_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_3_RESETVAL      (0x00000000u)

/* GLB_REG_4 */

#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_4_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_4_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_4_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_4_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_4_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_4_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_4_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_4_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_4_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_4_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_4_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_4_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_4_RESETVAL      (0x00000000u)

/* GLB_REG_5 */

#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_5_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_5_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_5_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_5_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_5_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_5_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_5_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_5_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_5_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_5_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_5_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_5_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_5_RESETVAL      (0x00000000u)

/* GLB_REG_6 */

#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_6_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_6_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_6_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_6_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_6_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_6_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_6_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_6_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_6_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_6_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_6_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_6_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_6_RESETVAL      (0x00000000u)

/* GLB_REG_7 */

#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_7_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_7_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_7_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_7_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_7_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_7_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_7_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_7_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_7_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_7_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_7_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_7_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_7_RESETVAL      (0x00000000u)

/* CCDC_WR_0 */

#define CSL_VPSS_CCDC_WR_0_BYTE_CNT_MASK (0x3FC00000u)
#define CSL_VPSS_CCDC_WR_0_BYTE_CNT_SHIFT (0x00000016u)
#define CSL_VPSS_CCDC_WR_0_BYTE_CNT_RESETVAL (0x00000000u)

#define CSL_VPSS_CCDC_WR_0_DATA_READY_MASK (0x00200000u)
#define CSL_VPSS_CCDC_WR_0_DATA_READY_SHIFT (0x00000015u)
#define CSL_VPSS_CCDC_WR_0_DATA_READY_RESETVAL (0x00000000u)

/*----DATA_READY Tokens----*/
#define CSL_VPSS_CCDC_WR_0_DATA_READY_NO (0x00000000u)
#define CSL_VPSS_CCDC_WR_0_DATA_READY_YES (0x00000001u)

#define CSL_VPSS_CCDC_WR_0_DATA_SENT_MASK (0x00100000u)
#define CSL_VPSS_CCDC_WR_0_DATA_SENT_SHIFT (0x00000014u)
#define CSL_VPSS_CCDC_WR_0_DATA_SENT_RESETVAL (0x00000000u)

/*----DATA_SENT Tokens----*/
#define CSL_VPSS_CCDC_WR_0_DATA_SENT_NO  (0x00000000u)
#define CSL_VPSS_CCDC_WR_0_DATA_SENT_YES (0x00000001u)

#define CSL_VPSS_CCDC_WR_0_ADDR_MASK     (0x000FFFFFu)
#define CSL_VPSS_CCDC_WR_0_ADDR_SHIFT    (0x00000000u)
#define CSL_VPSS_CCDC_WR_0_ADDR_RESETVAL (0x00000000u)

#define CSL_VPSS_CCDC_WR_0_RESETVAL      (0x00000000u)

/* CCDC_WR_1 */

#define CSL_VPSS_CCDC_WR_1_BYTE_CNT_MASK (0x3FC00000u)
#define CSL_VPSS_CCDC_WR_1_BYTE_CNT_SHIFT (0x00000016u)
#define CSL_VPSS_CCDC_WR_1_BYTE_CNT_RESETVAL (0x00000000u)

#define CSL_VPSS_CCDC_WR_1_DATA_READY_MASK (0x00200000u)
#define CSL_VPSS_CCDC_WR_1_DATA_READY_SHIFT (0x00000015u)
#define CSL_VPSS_CCDC_WR_1_DATA_READY_RESETVAL (0x00000000u)

/*----DATA_READY Tokens----*/
#define CSL_VPSS_CCDC_WR_1_DATA_READY_NO (0x00000000u)
#define CSL_VPSS_CCDC_WR_1_DATA_READY_YES (0x00000001u)

#define CSL_VPSS_CCDC_WR_1_DATA_SENT_MASK (0x00100000u)
#define CSL_VPSS_CCDC_WR_1_DATA_SENT_SHIFT (0x00000014u)
#define CSL_VPSS_CCDC_WR_1_DATA_SENT_RESETVAL (0x00000000u)

/*----DATA_SENT Tokens----*/
#define CSL_VPSS_CCDC_WR_1_DATA_SENT_NO  (0x00000000u)
#define CSL_VPSS_CCDC_WR_1_DATA_SENT_YES (0x00000001u)

#define CSL_VPSS_CCDC_WR_1_ADDR_MASK     (0x000FFFFFu)
#define CSL_VPSS_CCDC_WR_1_ADDR_SHIFT    (0x00000000u)
#define CSL_VPSS_CCDC_WR_1_ADDR_RESETVAL (0x00000000u)

#define CSL_VPSS_CCDC_WR_1_RESETVAL      (0x00000000u)