cslr_vpss_001.h

TI达芬奇dm644x各硬件模块测试代码

#ifndef _CSLR_VPSS_1_H_
#define _CSLR_VPSS_1_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_vpss_1.h
 * 
 * \brief This file contains the Register Desciptions for VPSS
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 PCR;
    volatile Uint32 GLB_REG_0;
    volatile Uint32 GLB_REG_1;
    volatile Uint32 GLB_REG_2;
    volatile Uint32 GLB_REG_3;
    volatile Uint32 GLB_REG_4;
    volatile Uint32 GLB_REG_5;
    volatile Uint32 GLB_REG_6;
    volatile Uint32 GLB_REG_7;
    volatile Uint32 CCDC_WR_0;
    volatile Uint32 CCDC_WR_1;
    volatile Uint32 CCDC_WR_2;
    volatile Uint32 CCDC_WR_3;
    volatile Uint32 CCDC_FP_RD_0;
    volatile Uint32 CCDC_FP_RD_1;
    volatile Uint32 PRV_RD_0;
    volatile Uint32 PRV_RD_1;
    volatile Uint32 PRV_RD_2;
    volatile Uint32 PRV_RD_3;
    volatile Uint32 PRV_WR_0;
    volatile Uint32 PRV_WR_1;
    volatile Uint32 PRV_WR_2;
    volatile Uint32 PRV_WR_3;
    volatile Uint32 PRV_DK_RD_0;
    volatile Uint32 PRV_DK_RD_1;
    volatile Uint32 PRV_DK_RD_2;
    volatile Uint32 PRV_DK_RD_3;
    volatile Uint32 RESZ_RD_0;
    volatile Uint32 RESZ_RD_1;
    volatile Uint32 RESZ_RD_2;
    volatile Uint32 RESZ_RD_3;
    volatile Uint32 RESZ1_WR_0;
    volatile Uint32 RESZ1_WR_1;
    volatile Uint32 RESZ1_WR_2;
    volatile Uint32 RESZ1_WR_3;
    volatile Uint32 RESZ2_WR_0;
    volatile Uint32 RESZ2_WR_1;
    volatile Uint32 RESZ2_WR_2;
    volatile Uint32 RESZ2_WR_3;
    volatile Uint32 RESZ3_WR_0;
    volatile Uint32 RESZ3_WR_1;
    volatile Uint32 RESZ3_WR_2;
    volatile Uint32 RESZ3_WR_3;
    volatile Uint32 RESZ4_WR_0;
    volatile Uint32 RESZ4_WR_1;
    volatile Uint32 RESZ4_WR_2;
    volatile Uint32 RESZ4_WR_3;
    volatile Uint32 HIST_RD_0;
    volatile Uint32 HIST_RD_1;
    volatile Uint32 AF_WR_0;
    volatile Uint32 AF_WR_1;
    volatile Uint32 AEAWB_WR_0;
    volatile Uint32 AEAWB_WR_1;
    volatile Uint32 OSD_V0_RD_0;
    volatile Uint32 OSD_V0_RD_1;
    volatile Uint32 OSD_V0_RD_2;
    volatile Uint32 OSD_V0_RD_3;
    volatile Uint32 OSD_V1_RD_0;
    volatile Uint32 OSD_V1_RD_1;
    volatile Uint32 OSD_V1_RD_2;
    volatile Uint32 OSD_V1_RD_3;
    volatile Uint32 OSD_O0_RD_0;
    volatile Uint32 OSD_O0_RD_1;
    volatile Uint32 OSD_O1_RD_2;
    volatile Uint32 OSD_O1_RD_3;
    volatile Uint32 SDR_REQ_EXP;
    volatile Uint32 TEST_CNT;
    volatile Uint32 MISR;
} CSL_VpssRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID */

#define CSL_VPSS_PID_TID_MASK            (0x00FF0000u)
#define CSL_VPSS_PID_TID_SHIFT           (0x00000010u)
#define CSL_VPSS_PID_TID_RESETVAL        (0x00000001u)

#define CSL_VPSS_PID_CID_MASK            (0x0000FF00u)
#define CSL_VPSS_PID_CID_SHIFT           (0x00000008u)
#define CSL_VPSS_PID_CID_RESETVAL        (0x000000FBu)

#define CSL_VPSS_PID_PREV_MASK           (0x000000FFu)
#define CSL_VPSS_PID_PREV_SHIFT          (0x00000000u)
#define CSL_VPSS_PID_PREV_RESETVAL       (0x00000000u)

#define CSL_VPSS_PID_RESETVAL            (0x0001FB00u)

/* PCR */

#define CSL_VPSS_PCR_CCDC_WBL_O_MASK     (0x00800000u)
#define CSL_VPSS_PCR_CCDC_WBL_O_SHIFT    (0x00000017u)
#define CSL_VPSS_PCR_CCDC_WBL_O_RESETVAL (0x00000000u)

/*----CCDC_WBL_O Tokens----*/
#define CSL_VPSS_PCR_CCDC_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_CCDC_WBL_O_OVERFLOW (0x00000001u)

#define CSL_VPSS_PCR_PRV_WBL_O_MASK      (0x00400000u)
#define CSL_VPSS_PCR_PRV_WBL_O_SHIFT     (0x00000016u)
#define CSL_VPSS_PCR_PRV_WBL_O_RESETVAL  (0x00000000u)

/*----PRV_WBL_O Tokens----*/
#define CSL_VPSS_PCR_PRV_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_PRV_WBL_O_OVERFLOW  (0x00000001u)

#define CSL_VPSS_PCR_RSZ1_WBL_O_MASK     (0x00200000u)
#define CSL_VPSS_PCR_RSZ1_WBL_O_SHIFT    (0x00000015u)
#define CSL_VPSS_PCR_RSZ1_WBL_O_RESETVAL (0x00000000u)

/*----RSZ1_WBL_O Tokens----*/
#define CSL_VPSS_PCR_RSZ1_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_RSZ1_WBL_O_OVERFLOW (0x00000001u)

#define CSL_VPSS_PCR_RSZ2_WBL_O_MASK     (0x00100000u)
#define CSL_VPSS_PCR_RSZ2_WBL_O_SHIFT    (0x00000014u)
#define CSL_VPSS_PCR_RSZ2_WBL_O_RESETVAL (0x00000000u)

/*----RSZ2_WBL_O Tokens----*/
#define CSL_VPSS_PCR_RSZ2_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_RSZ2_WBL_O_OVERFLOW (0x00000001u)

#define CSL_VPSS_PCR_RSZ3_WBL_O_MASK     (0x00080000u)
#define CSL_VPSS_PCR_RSZ3_WBL_O_SHIFT    (0x00000013u)
#define CSL_VPSS_PCR_RSZ3_WBL_O_RESETVAL (0x00000000u)

/*----RSZ3_WBL_O Tokens----*/
#define CSL_VPSS_PCR_RSZ3_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_RSZ3_WBL_O_OVERFLOW (0x00000001u)

#define CSL_VPSS_PCR_RSZ4_WBL_O_MASK     (0x00040000u)
#define CSL_VPSS_PCR_RSZ4_WBL_O_SHIFT    (0x00000012u)
#define CSL_VPSS_PCR_RSZ4_WBL_O_RESETVAL (0x00000000u)

/*----RSZ4_WBL_O Tokens----*/
#define CSL_VPSS_PCR_RSZ4_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_RSZ4_WBL_O_OVERFLOW (0x00000001u)

#define CSL_VPSS_PCR_AF_WBL_O_MASK       (0x00020000u)
#define CSL_VPSS_PCR_AF_WBL_O_SHIFT      (0x00000011u)
#define CSL_VPSS_PCR_AF_WBL_O_RESETVAL   (0x00000000u)

/*----AF_WBL_O Tokens----*/
#define CSL_VPSS_PCR_AF_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_AF_WBL_O_OVERFLOW   (0x00000001u)

#define CSL_VPSS_PCR_AEW_WBL_O_MASK      (0x00010000u)
#define CSL_VPSS_PCR_AEW_WBL_O_SHIFT     (0x00000010u)
#define CSL_VPSS_PCR_AEW_WBL_O_RESETVAL  (0x00000000u)

/*----AEW_WBL_O Tokens----*/
#define CSL_VPSS_PCR_AEW_WBL_O_NOOVERFLOW (0x00000000u)
#define CSL_VPSS_PCR_AEW_WBL_O_OVERFLOW  (0x00000001u)

#define CSL_VPSS_PCR_DMA_PRI_MASK        (0x0000000Fu)
#define CSL_VPSS_PCR_DMA_PRI_SHIFT       (0x00000000u)
#define CSL_VPSS_PCR_DMA_PRI_RESETVAL    (0x00000000u)

#define CSL_VPSS_PCR_RESETVAL            (0x00000000u)

/* GLB_REG_0 */

#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_0_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_0_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_0_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_0_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_0_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_0_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_0_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_0_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_0_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_0_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_0_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_0_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_0_RESETVAL      (0x00000000u)

/* GLB_REG_1 */

#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_1_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_1_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_1_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_1_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_1_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_1_DIRECTION_READ (0x00000000u)
#define CSL_VPSS_GLB_REG_1_DIRECTION_WRITE (0x00000001u)

#define CSL_VPSS_GLB_REG_1_VALID_MASK    (0x00000001u)
#define CSL_VPSS_GLB_REG_1_VALID_SHIFT   (0x00000000u)
#define CSL_VPSS_GLB_REG_1_VALID_RESETVAL (0x00000000u)

/*----VALID Tokens----*/
#define CSL_VPSS_GLB_REG_1_VALID_NOTVALID (0x00000000u)
#define CSL_VPSS_GLB_REG_1_VALID_VALID   (0x00000001u)

#define CSL_VPSS_GLB_REG_1_RESETVAL      (0x00000000u)

/* GLB_REG_2 */

#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_MASK (0x00000180u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_SHIFT (0x00000007u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_RESETVAL (0x00000000u)

/*----SRC_DST_ID Tokens----*/
#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_RW_REQ_1 (0x00000000u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_RW_REQ_2 (0x00000001u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_RW_REQ_3 (0x00000002u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_ID_RW_REQ_4 (0x00000003u)

#define CSL_VPSS_GLB_REG_2_SRC_DST_M_MASK (0x0000007Cu)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_SHIFT (0x00000002u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_RESETVAL (0x00000000u)

/*----SRC_DST_M Tokens----*/
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_CCDC_OUT (0x00000000u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_CCDC_FAULTPIX_IN (0x00000001u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_PREV_IN (0x00000002u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_PREV_OUT (0x00000003u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_PREV_DKFRM_IN (0x00000004u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_RESZ_IN (0x00000005u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_RESZ_OUT_1 (0x00000006u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_RESZ_OUT_2 (0x00000007u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_RESZ_OUT_3 (0x00000008u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_RESZ_OUT_4 (0x00000009u)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_H3A_AF_OUT (0x0000000Bu)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_H3A_AE_AWB_OUT (0x0000000Cu)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_OSD_VIDWIN_0 (0x0000000Du)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_OSD_VIDWIN_1 (0x0000000Eu)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_OSD_BMPWIN_0 (0x0000000Fu)
#define CSL_VPSS_GLB_REG_2_SRC_DST_M_OSD_BMPWIN_1 (0x00000010u)

#define CSL_VPSS_GLB_REG_2_DIRECTION_MASK (0x00000002u)
#define CSL_VPSS_GLB_REG_2_DIRECTION_SHIFT (0x00000001u)
#define CSL_VPSS_GLB_REG_2_DIRECTION_RESETVAL (0x00000000u)

/*----DIRECTION Tokens----*/
#define CSL_VPSS_GLB_REG_2_DIRECTION_READ (0x00000000u)