csl_ccdc.h

TI达芬奇dm644x各硬件模块测试代码

*
* All fields needed for Horizontal & Vertical Pixel and Start Info for the SDRAM 
* output port are present in this structure.
*/
typedef struct CSL_CcdcSdrOutSizeConfig_{
	/** Start Pixel, horizontal */
	Uint16 startPixelH;
	/** Number of pixels, horizontal 
		(note: CSL will write numPixelsH-1 to register as per TRM) */
	Uint16 numPixelsH;
	/** Start Line, Vertical (Field 0) */
	Uint16 startLineV0;
	/** Start Line, Vertical (Field 1) */
	Uint16 startLineV1;
	/** Number of lines, vertical 
		(note: CSL will write numLinesV-1 to register as per TRM) */
	Uint16 numLinesV;
}CSL_CcdcSdrOutSizeConfig;

/** @brief CCDC Pixels per lines and Lines per Pixel Info structure.
*
* All fields needed for Pixels per line and lines per pixel are present 
* in this structure.  These parameters do not apply when HD & VD are inputs.
*/
typedef struct CSL_CcdcPixLinesConfig_{
	/** Pixels per Line 
	(note: CSL will write pixPerLine-1 to register as per TRM)*/
	Uint16 pixPerLine;
	/** Number of pixels, horizontal 
	(note: CSL will write halfLinesPerFm-1 to register as per TRM)*/
	Uint16 halfLinesPerFm;
}CSL_CcdcPixLinesConfig;


/** @brief SDRAM/DDRAM line offset Configuration structure
*
* All fields needed for SDRAM/DDRAM line offset are present in this structure.
*/
typedef struct CSL_CcdcSdramOffsetConfig_{
     /** Field Identification signal inverse: 0==> Non-inverse, 1==> Inverse*/
     Uint8 fieldIdInv;
     /** Line offset value of field ID=1 */
     Uint8 lnOffFID1;
     /** Line offset values of even line and even field ID = 0*/
     Uint8 lnOffEvLnEvFD;
     /** Line offset values of odd line and even field ID = 0*/
     Uint8 lnOffOddLnEvFD;
     /** Line offset values of even line and odd field ID = 1*/
     Uint8 lnOffEvLnOddFD;
     /** Line offset values of odd line and odd field ID = 1*/
     Uint8 lnOffOddLnOddFD;
}CSL_CcdcSdramOffsetConfig;


/** @brief Optical Black Clamping Configuration structure
*
* All fields needed for Optical Black Clamping are present in this structure.  This 
* feature applies to CCD raw data inputs.
*/
typedef struct CSL_CcdcOptBlackClampConfig_{
     /** Optical Black Sample length
			CSL_CCDC_CLAMP_1, 
			CSL_CCDC_CLAMP_2, 
			CSL_CCDC_CLAMP_4, 
			CSL_CCDC_CLAMP_8, 
			CSL_CCDC_CLAMP_16	*/
     Uint8 obSampLen;
     /** Optical Black sample lines
			CSL_CCDC_CLAMP_1, 
			CSL_CCDC_CLAMP_2, 
			CSL_CCDC_CLAMP_4, 
			CSL_CCDC_CLAMP_8, 
			CSL_CCDC_CLAMP_16	*/
     Uint8 obSampLns;
     /** Start pixel of optical black samples*/
     Uint16 obStart;
     /** Gain to apply to optical black average */
     Uint8 obGain;
}CSL_CcdcOptBlackClampConfig;

/** @brief CCD Color pattern Configuration structure
*
* All fields needed for CCD color pattern setup are present in this structure.  This
* feature applies to CCD raw data inputs.
*/
typedef struct CSL_CcdcColorPatternConfig_{

	/** Color Pattern Mapping
     *		row: line0 - line3
	 *		col: pixel_counter0 - pixel_counter3
	 *		Options:
	 *			CSL_CCDC_COLPTN_R_YE
	 *			CSL_CCDC_COLPTN_GR_CY
	 *			CSL_CCDC_COLPTN_GB_G
	 *			CSL_CCDC_COLPTN_B_MG
	 */
	Uint8 colPatn[4][4];
}CSL_CcdcColorPatternConfig;

/** @brief  Black Compensation structure
*
*  All fields needed for Black Compensation are present in this structure. This
* feature applies to CCD raw data inputs.
*/
typedef struct CSL_CcdcBlackCmpConfig_{
    /** Black level compensation for R/Ye pixels (-128:+127)*/
     Int8 rye;
    /** Black level compensation for Gr/Cy pixels (-128:+127)*/
     Int8 grcy;
    /** Black level compensation for Gb/G pixels (-128:+127)*/
     Int8 gbg;
    /** Black level compensation for B/Mg pixels (-128:+127)*/
     Int8 bmg;
}CSL_CcdcBlackCmpConfig;

/** @brief Culling Info structure.
*
* All fields needed for Culling in the Horizontal & Vertical directions are 
* present in this structure.
*/
typedef struct CSL_CcdcCullingControl_{
	/** Horizontal culling pattern for even line, 8-bit mask:
	      0==> Cull, 1==> Retain */
	Uint8 cullHEven;
	/** Horizontal culling pattern for odd line, 8-bit mask:
	      0==> Cull, 1==> Retain */
	Uint8 cullHOdd;
	/** Vertical culling pattern, 8-bit mask: 0==> Cull, 1==>Retain  */
	Uint8 cullVert;
}CSL_CcdcCullingControl;

/** @brief  Fault Pixel Correction structure
*
*  All fields needed for Fault Pixel Correction are present in this structure. This
* feature applies to CCD raw data inputs.
*/
typedef struct CSL_CcdcFPCConfig_{
     /** Enable the Fault Pixel Correction module */
     Uint8 fpcEnable;
     /** Number of fault pixels to be corrected in a frame*/
     Uint16 fpNum;
     /** Starting SDRAM/DDRAM address of the fault pixel correction entries
		(note: must be aligned to a 64 byte boundary) */
     Uint32 *fpcAddr;
}CSL_CcdcFPCConfig;

/** @brief  VD Interrupt Timing structure
*
*  All fields needed for VD Interrupt Timing  are present in this structure.
*/
typedef struct CSL_CcdcVdIntTiming_{
     /** VD Interrupt ID: CSL_CCDC_VDINT0, CSL_CCDC_VDINT1 */
     Uint16 vdIntId;
     /** VD Interrupt Timing: number of lines from VD when interrupt 'vdIntId' should occur
		(note: CSL will write numLines-1 to register as per TRM)*/
     Uint16 numLines;
}CSL_CcdcVdIntTiming;

/** @brief  A-Law Config structure
*
*  All fields needed for A-Law Config  are present in this structure. This
* feature applies to CCD raw data inputs.
*/
typedef struct CSL_CcdcALawConfig_{
     /** Gamma (A-Law) enable: CSL_CCDC_ALAW_ENABLE, CSL_CCDC_ALAW_DISABLE  */
     Uint8 sdramALAWEnable;
     /** 10 bit input select for A-LAW table: 
		CSL_CCDC_BITS_15_6, 
		CSL_CCDC_BITS_14_5, 
		CSL_CCDC_BITS_13_4, 
		CSL_CCDC_BITS_12_3, 
		CSL_CCDC_BITS_11_2, 
		CSL_CCDC_BITS_10_1, 
		CSL_CCDC_BITS_09_0 */
     Uint8 widthInput;
}CSL_CcdcALawConfig;

/** @brief  YCC Configuration structure
*
*  Fields which apply to YCC Input Mode data control.
*/
typedef struct CSL_CcdcYccInputConfig_{
     /** Y and C input swap: CSL_CCDC_YCIN_SWAP, CSL_CCDC_NO_YCIN_SWAP */
     Uint8 ycinSwap;
     /** Location of Y signal when YCbCr 8-bit data is input: CSL_CCDC_Y8POS_EVENPIXEL, CSL_CCDC_Y8POS_ODDPIXEL */
     Uint8 y8pos;
     /** MSB of Chroma input signal stored to SDRAM inverted: CSL_CCDC_MSB_IN_NORMAL, CSL_CCDC_MSB_IN_INVERTED*/
     Uint8 msbinvi;
}CSL_CcdcYccInputConfig;

/** @brief  REC656 Configuration structure
*
*  Fields which apply to REC656 input mode.
*/
typedef struct CSL_CcdcRec656Config_{
     /** Data width in CCIR656 input mode: CSL_CCDC_REC656_8_BITS, CSL_CCDC_REC656_10_BITS */
     Uint8 bitWidth;
	 /** FVH error correction enable: CSL_CCDC_REC656_ECCFVH_ENABLE, CSL_CCDC_REC656_ECCFVH_DISABLE */
	 Uint8 eccFvhEn;
}CSL_CcdcRec656Config;

/** @brief  Video Port Configuration structure
*
*  Fields which apply to the Video Port configuration are present in this structure.
*/
typedef struct CSL_CcdcVpConfig_{
     /** Video port data ready frequency: 
		CSL_CCDC_VPIF_FRQ_ONE_HALF, 
		CSL_CCDC_VPIF_FRQ_ONE_THIRD,  
		CSL_CCDC_VPIF_FRQ_ONE_FOURTH, 
		CSL_CCDC_VPIF_FRQ_ONE_FIFTH, 
		CSL_CCDC_VPIF_FRQ_ONE_SIXTH 	*/
     Uint8 vpifFreq;
     /** 10-bit input select for video port: 
		CSL_CCDC_BITS_15_6, 
		CSL_CCDC_BITS_14_5, 
		CSL_CCDC_BITS_13_4, 
		CSL_CCDC_BITS_12_3, 
		CSL_CCDC_BITS_11_2, 
		CSL_CCDC_BITS_10_1, 
		CSL_CCDC_BITS_09_0 	 */
     Uint8 vpin;
}CSL_CcdcVpConfig;

/** @brief  Data Reformatter/Video Port Configuration structure
*
*  All fields needed for Data Reformatter/Video Port input sizes are present in this structure.
*/
typedef struct CSL_CcdcFmtVpInConfig_{
     /** Start pixel horizontal from start of HD */
     Uint16 fmtsph;
     /** Number of pixels in horizontal direction */
     Uint16 fmtlnh;
     /** Start line from start of VD */
     Uint16 fmtslv;
     /** Number of lines in vertical direction */
     Uint16 fmtlnv;
}CSL_CcdcFmtVpInConfig;

/** @brief  Data Reformatter Configuration structure
*
*  Fields which apply to the Data Reformatter configuration are present in this structure.
*/
typedef struct CSL_CcdcFmtConfig_{

     /** Number of program entries in even line (1:8) 
		(note: CSL will write plenEven-1 to register as per TRM)*/
     Uint8 plenEven;
     /** Number of program entries in odd line (1:8) 
		(note: CSL will write plenOdd-1 to register as per TRM)*/
     Uint8 plenOdd;
     /** Number of output lines from 1 input line */
     Uint8 lNum;
     /** Line alternating mode */
     Uint8 lnalt;

     /** Output line for data formatter addresses 0-7 (valid range: 1-4)
		(note: CSL will write fmtAddrLine[i]-1 to register as per TRM)*/
     Uint8 fmtAddrLine[8];
     /** Initial address value for Data formatter addresses 0-7*/
     Uint16 fmtAddrInit[8];
}CSL_CcdcFmtConfig;

/** @brief  Program entries Configuration structure
*
*  All fields needed for Program entries (for even and odd lines) configuration 
*  are present in this structure.
*/
typedef struct CSL_CcdcFmtProgConfig_{
    /** Address update: valid range (0:7) corresponding to addresses 0-7  */
     Uint8 addr[16];
	 /** Address increment/decrement: CSL_CCDC_AUTO_INC, CSL_CCDC_AUTO_DEC  */
	 Uint8 update[16];
}CSL_CcdcFmtProgConfig;

/** @brief  Video port output structure
*
*  All fields needed for Video port output sizes are present in this structure.
*/
typedef struct CSL_CcdcVpOutConfig_{
     /** Number of vert. lines to clock out the video port  */
     Uint16 vertNum;
     /** Number of horz. pixels to clock out the video port */
     Uint16 horzNum;
     /** Horz. start pixel in each output line */
     Uint8 horzStart;
}CSL_CcdcVpOutConfig;

/** @brief This has all the fields required to configure CCDC at Power Up
 *  (After a Hardware Reset) or a Soft Reset
 *
 *  This structure is used to setup or obtain existing setup of
 *  CCDC using @a CSL_ccdcHwSetup() function.
 */
typedef struct CSL_CcdcHwSetup_ {