csl_ccdc.h

TI达芬奇dm644x各硬件模块测试代码

#define CSL_CCDC_VPIF_FRQ_ONE_THIRD				(CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_THIRDHALF)
/** For indicating that video port data ready frequency is 1/4   */
#define CSL_CCDC_VPIF_FRQ_ONE_FOURTH			(CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_FOURTHHALF)
/** For indicating that video port data ready frequency is 1/5   */
#define CSL_CCDC_VPIF_FRQ_ONE_FIFTH				(CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_FIFTHHALF)
/** For indicating that video port data ready frequency is 1/6   */
#define CSL_CCDC_VPIF_FRQ_ONE_SIXTH				(CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_SIXTHHALF)

/** For indicating that VDINT0 is selected   */
#define CSL_CCDC_VDINT0							(0x00000000u)
/** For indicating that VDINT1 is selected   */
#define CSL_CCDC_VDINT1							(0x00000001u)

/** For indicating that the update specifier is auto increment   */
#define CSL_CCDC_AUTO_INC						(0x00000000u)
/** For indicating that the update specifier is auto decrement   */
#define CSL_CCDC_AUTO_DEC						(0x00000001u)


/**************************************************************************\
* CCDC global typedef declarations
\**************************************************************************/

/** @brief Enumeration for queries passed to @a CSL_ccdcGetHwStatus()
 *
 * This is used to get the status of different operations or to get the
 * existing setup of CCDC.
 */
typedef enum {
  /** Get the CCDC module ID and revision numbers (response type: @a (CSL_CcdcRevStatus*)) */
  CSL_CCDC_QUERY_REV_ID = 1,
  /** Get the CCDC busy status (response type: @a Uint16 *)        */
  CSL_CCDC_QUERY_IS_BUSY,
  /** Get the Field status information (response type: @a Uint16 *)    */
  CSL_CCDC_QUERY_FIELD_STATUS,
  /** Get the Fault Pixel Correction error status (response type: @a Uint16 *)    */
  CSL_CCDC_QUERY_FPC_ERROR,
  /** Called after settings are set, checks to see if any interdependant 
	  setting restrictions are violated (response type: @a (Uint32*) ) 
 	  If there are no violations, the function will return a CSL_SOK condition
 	  and the response value will be equal to 0.  If there are any violations, 
 	  the function will return the CSL_ESYS_FAIL error and the response value will
 	  have bits set which indicate any violations found.  The following are the 
 	  violation codes for the bits of the response variable:
		
		 0: External WEN will not work when VP2SDR path is enabled
		 1: In line alternating mode, the vertical start and number must be even
		 2: At least one of the formatter initial addresses is beyond the max value
		 3. The horizontal number for the video port is beyond the max value
		 4. The vertical number for the video port is beyond the max value
		 5: The video port needs to be enabled if the formatter is enabled
		 6: In ycc input mode, the COLPTN should be set to 0s.
		 7: In ycc input mode, the BLKCMP should be set to 0s.
		 8: In ycc input mode, the fault pixel correction should be disabled.
		 9: In ycc input mode, the Video port should be disabled.
		10: In ycc input mode, the Formatter should be disabled.
		11: In ycc input mode, the VP2SDR should be disabled.
		12: In ycc input mode, the low pass filter should be disabled.
		13: In ycc input mode, the ALAW should be disabled.
		14: WARNING: In ycc input mode, neither the Resizer output or the SDRAM output is enabled.
		15: In raw input mode, the resizer output path should not be enabled.
		16 - 31: RESERVED
  */
  CSL_CCDC_QUERY_CHECK_SETTINGS

} CSL_CcdcHwStatusQuery;


/** @brief Enumeration for queries passed to @a CSL_ccdcHwControl()
 *
 * This is used to select the commands to control the operations
 * existing setup of CCDC. The arguments to be passed with each
 * enumeration if any are specified next to the enumeration.
 */
 typedef enum {
	/** Enable/Disable the CCDC module : argument @a (Uint16*)
	    CSL_CCDC_ENABLE, CSL_CCDC_DISABLE*/
	CSL_CCDC_CMD_ENABLE = 1,
	/** Set the mode : argument @a (CSL_CcdcMode *) */
	CSL_CCDC_CMD_SET_MODE,
	/** Enable/Disable the VD/HD : argument @a (Uint16*)
	    CSL_CCDC_VD_HD_ENABLE, CSL_CCDC_VD_HD_DISABLE*/
	CSL_CCDC_CMD_VD_HD_ENABLE,
	/** Enable/Disable the CCD formatter: argument @a (Uint16*) 
		CSL_CCDC_FMT_ENABLE, CSL_CCDC_FMT_DISABLE */
	CSL_CCDC_CMD_FMT_ENABLE,
	/** Configure the CCD formatter/Video Port input size: argument @a (CSL_CcdcFmtVpInConfig *) */
	CSL_CCDC_CMD_SET_FMT_VP_IN_SIZE,
	/** Set the video port output sizes: argument @a (CSL_CcdcVpOutConfig *)  */
	CSL_CCDC_CMD_SET_VP_OUT_SIZE,
	/** Enable/Disable the Video port: argument @a (Uint16*) 
		CSL_CCDC_VIDEO_PORT_ENABLE, CSL_CCDC_VIDEO_PORT_DISABLE */
	CSL_CCDC_CMD_VP_ENABLE,
	/** Enable/Disable the data path from the Video port to the 
	 *  SDRAM output port : argument @a (Uint16*)
	    CSL_CCDC_VP2SDR_ENABLE, CSL_CCDC_VP2SDR_DISABLE*/
	CSL_CCDC_CMD_VP2SDR_ENABLE,
	/** Enable/Disable the SDRAM output port : argument @a (Uint16*)
	    CSL_CCDC_SDRAM_OUT_ENABLE, CSL_CCDC_SDRAM_OUT_DISABLE*/
	CSL_CCDC_CMD_SDRAM_OUTPUT_ENABLE,
	/** Set the SDRAM starting address : argument @a (Uint32*) 
		(note: must be aligned to a 32 byte boundary) */
	CSL_CCDC_CMD_SET_SDRAM_ADDR,
	/** Set the SDRAM address offset: argument @a (Uint16*) 
		(note: must be aligned to a 32 byte boundary)*/
	CSL_CCDC_CMD_SET_SDRAM_OFFSET,
	/** Configure the Horz and Vert parameters of the data at the SDRAM
		output port: argument @a (CSL_CcdcSdrOutSizeConfig *)  */
	CSL_CCDC_CMD_SET_SDRAM_OUT_SIZE,
	/** Configure the number of pixels per line and lines 
	 *  per frame (when HD & VD are outputs): argument @a (CSL_CcdcPixLinesConfig *)  */
	CSL_CCDC_CMD_SET_PIX_LINES,
	/** Set the SYNC and Mode : argument @a (CSL_CcdcSyncModeConfig *) */
	CSL_CCDC_CMD_SET_SYNC_MODE,
	/** Culling Control : argument @a (CSL_CcdcCullingControl *) */
	CSL_CCDC_CMD_SET_CULLING_CONTROL,
	/** Enable/Disable the Optical Black Clamp module: argument @a (Uint16*) 
	    CSL_CCDC_CLAMP_ENABLE, CSL_CCDC_CLAMP_DISABLE */
	CSL_CCDC_CMD_OPT_BLACK_CLAMP_ENABLE,
    /** Set the Optical Black Clamping parameters : argument 
        @a (CSL_CcdcOptBlackClampConfig *)  */
	CSL_CCDC_CMD_SET_OPT_BLACK_CLAMP,
	/** Set the black compensation parameters: argument @a (CSL_CcdcBlackCmpConfig *) */
	CSL_CCDC_CMD_SET_BLACK_COMP,
	/** Set the fault pixel correction settings : argument @a (CSL_CcdcFPCConfig *) */
	CSL_CCDC_CMD_SET_FPC,
    /** Set the VD Interrupt Timing : argument @a (CSL_CcdcVdIntTiming *) */
	CSL_CCDC_CMD_SET_VD_INT,
	/** Set the A-law parameters: argument @a (CSL_CcdcALawConfig *) */
	CSL_CCDC_CMD_SET_ALAW_CONFIG,
    /** Enable the REC656 interface:  argument @a (Uint16*) 
		CSL_CCDC_REC656_ENABLE, CSL_CCDC_REC656_DISABLE */
	CSL_CCDC_CMD_REC656_ENABLE,
	/** Enable/Disable the FVH Error correction: : argument @a (Uint16*) 
		CSL_CCDC_REC656_ECCFVH_ENABLE, CSL_CCDC_REC656_ECCFVH_DISABLE */
	CSL_CCDC_CMD_REC656_ECCFVH_ENABLE

} CSL_CcdcHwControlCmd;

/** @brief Enumeration for different input modes
 *
 * This is used to set the input mode 
 */
typedef enum {
	/** CCD Raw data input      */
	CSL_CCDC_IN_RAW_DATA =		CSL_CCDC_SYN_MODE_INPMOD_CCDRAW,
	/** YCbCr 16-bit	*/
	CSL_CCDC_IN_YCbCr_16_BIT =	CSL_CCDC_SYN_MODE_INPMOD_YCBCR16,
	/** YCbCr 8-bit		*/
	CSL_CCDC_IN_YCbCr_8_BIT =	CSL_CCDC_SYN_MODE_INPMOD_YCBCR8,	
	/** REC656			*/
	CSL_CCDC_IN_REC656	
					
} CSL_CcdcInputSelect;

/** @brief Enumeration for error bit codes from the @a CSL_ccdcCheckSettings() API
 *
 * This is used to identify the error bit codes fron the @a CSL_ccdcCheckSettings() API
 */
typedef enum {
	/** Indicates that there are no errors, all restrictions are met		*/
	CSL_CCDC_ERR_NO_ERRORS							= 0x00000000,
	/** Bit 0: External WEN will not work when VP2SDR path is enabled		*/
	CSL_CCDC_ERR_EXWEN_NOT_ALLOWED_WHEN_VP2SDR		= 0x00000001,
	/** Bit 1: In line alternating mode, the vertical start and number must be even		*/
	CSL_CCDC_ERR_FMT_LNALT_VERT_NOT_EVEN			= 0x00000002,
	/** Bit 2: At least one of the formatter initial addresses is beyond the max value	*/
	CSL_CCDC_ERR_FMT_ADDR_INIT_OVER_MAX_VALUE		= 0x00000004,
	/** Bit 3. The horizontal number for the video port is beyond the max value			*/
	CSL_CCDC_ERR_VP_HORZ_NUM_OVER_MAX_VALUE			= 0x00000008,
	/** Bit 4. The vertical number for the video port is beyond the max value			*/
	CSL_CCDC_ERR_VP_VERT_NUM_OVER_MAX_VALUE			= 0x00000010,
	/** Bit 5: The video port needs to be enabled if the formatter is enabled			*/
	CSL_CCDC_ERR_VP_NOT_ENABLED						= 0x00000020,
	/** Bit 6: In ycc input mode, the COLPTN should be set to 0s.			*/
	CSL_CCDC_ERR_YCC_INPUT_COLPTN_SET				= 0x00000040,
	/** Bit 7: In ycc input mode, the BLKCMP should be set to 0s.			*/
	CSL_CCDC_ERR_YCC_INPUT_BLKCMP_SET				= 0x00000080,
	/** Bit 8: In ycc input mode, the fault pixel correction should be disabled.		*/
	CSL_CCDC_ERR_YCC_INPUT_FPC_SET					= 0x00000100,
	/** Bit 9: In ycc input mode, the Video port should be disabled.		*/
	CSL_CCDC_ERR_YCC_INPUT_VPEN_SET					= 0x00000200,
	/** Bit10: In ycc input mode, the Formatter should be disabled.			*/
	CSL_CCDC_ERR_YCC_INPUT_FMTEN_SET				= 0x00000400,
	/** Bit11: In ycc input mode, the VP2SDR should be disabled.			*/
	CSL_CCDC_ERR_YCC_INPUT_VP2SDR_SET				= 0x00000800,
	/** Bit12: In ycc input mode, the low pass filter should be disabled.	*/
	CSL_CCDC_ERR_YCC_INPUT_LPF_SET					= 0x00001000,
	/** Bit13: In ycc input mode, the ALAW should be disabled.				*/
	CSL_CCDC_ERR_YCC_INPUT_ALAW_SET					= 0x00002000,
	/** Bit14: WARNING: In ycc input mode, neither the Resizer output or the SDRAM output is enabled.      */
	CSL_CCDC_ERR_YCC_INPUT_OUTPUT_NOT_SET_WARNING	= 0x00004000,
	/** Bit15: In raw input mode, the resizer output path should not be enabled.		*/
	CSL_CCDC_ERR_RAW_INPUT_RSZ_OUTPUT_SET			= 0x00008000
} CSL_CcdcErrorBits;


/** @brief This object contains the reference to the instance of CCDC opened
 *  using the @a CSL_ccdcOpen().
 *
 *  The pointer to this, is passed to all CCDC CSL APIs.
 */
typedef struct CSL_CcdcObj {
	/** This is the mode which the CSL instance is opened     */
	CSL_OpenMode openMode;
	/** This is a unique identifier to the instance of CCDC being
	 *  referred to by this object
	 */
	CSL_Uid uid;
	/** This is the variable that contains the current state of a
	 *  resource being shared by current instance of CCDC with
        *  other peripherals
        */
	CSL_Xio xio;
	/** This is a pointer to the registers of the instance of CCDC
         *  referred to by this object
        */
	CSL_CcdcRegsOvly regs;
	/** This is the instance of CCDC being referred to by this object  */
	CSL_CcdcNum perNum;
}CSL_CcdcObj;

typedef struct CSL_CcdcObj *CSL_CcdcHandle;

/** @brief  Mode set control structure
*
*  All fields needed for enabling or disabling various hardware modes  
*  are present in this structure.
*/
typedef struct CSL_CcdcMode_{
     /** VD/HD Enable: CSL_CCDC_VD_HD_ENABLE, CSL_CCDC_VD_HD_DISABLE */
	 Uint8 vdHdEn;
     /** 3-tap Low-Pass Filter: CSL_CCDC_LPF_ON, CSL_CCDC_LPF_OFF */
	 Uint8 lowPassFilterEn;
     /** Optical Black Clamp En: CSL_CCDC_CLAMP_ENABLE, CSL_CCDC_CLAMP_DISABLE */
	 Uint8 blackClampEn;
     /** CCD formatter enable: CSL_CCDC_FMT_ENABLE, CSL_CCDC_FMT_DISABLE */
     Uint8 fmtEn;
     /** Video port enable: CSL_CCDC_VIDEO_PORT_ENABLE, CSL_CCDC_VIDEO_PORT_DISABLE */
     Uint8 vpEn;
     /** Video port to sdram port enable: CSL_CCDC_SDRAM_OUT_ENABLE, CSL_CCDC_SDRAM_OUT_DISABLE */
     Uint8 vp2SdramEn;
     /** Sdram output port enable: CSL_CCDC_VP2SDR_ENABLE, CSL_CCDC_VP2SDR_DISABLE */
     Uint8 sdramOutEn;
}CSL_CcdcMode;


/** @brief SYNC and Mode set Control structure.
*
* All fields needed for synchronization with external inputs/outputs to the CCDC
* are present in this structure.
*/
typedef struct CSL_CcdcSyncModeConfig_{
	/** CCD Data bit width for RAW data input */
	Uint8 dataBitWidth;
	/** Pack data stored to SDRAM to 8 bits/pixel: CSL_CCDC_PACK8_16BITS_PIXEL, CSL_CCDC_PACK8_8BITS_PIXEL */
	Uint8 pack8;
    /** Byte swap data stored to SDRAM: CSL_CCDC_DONT_SWAPBYTES, CSL_CCDC_SWAPBYTES*/
    Uint8 byteSwap;
    /** Enable latching function on internal VSYNC: CSL_CCDC_LATCHED_ON_VSYNC, CSL_CCDC_NOT_LATCHED_ON_VSYNC */
    Uint8 vdLatch;
	/** Sensor Field Mode: CSL_CCDC_FLDMODE_PROGRESSIVE, CSL_CCDC_FLDMODE_INTERLACED */
	Uint8 fieldMode;
	/** CCD data polarity: CSL_CCDC_DATAPOL_NORMAL, CSL_CCDC_DATAPOL_ONES_COMPLEMENT */
	Uint8 dataPolarity;
	/** External WEN selection: CSL_CCDC_EXTERNAL_WEN, CSL_CCDC_NO_EXTERNAL_WEN */
	Uint8 exWEN;
    /** Specifies CCD valid area: CSL_CCDC_WENLOG_AND, CSL_CCDC_WENLOG_OR */
    Uint8 wenlog;
	/** Field Indicator Polarity: CSL_CCDC_FLD_POL_POSITIVE, CSL_CCDC_FLD_POL_NEGATIVE */
	Uint8 fieldPolarity;
	/** HD Sync Polarity: CSL_CCDC_HD_POL_POSITIVE, CSL_CCDC_HD_POL_NEGATIVE */
	Uint8 hdSyncPolarity;
	/** VD Sync Polarity: CSL_CCDC_VD_POL_POSITIVE, CSL_CCDC_VD_POL_NEGATIVE */
	Uint8 vdSyncPolarity;
    /** Setting of FID detection function:
		CSL_CCDC_FID_LATCH_AT_VSYNC,
		CSL_CCDC_FID_NO_LATCH,
		CSL_CCDC_FID_LATCH_AT_VD_EDGE,
		CSL_CCDC_FID_LATCH_ON_VD_HD_PHASE */
    Uint8 fieldDetect;
	/** Field ID direction: CSL_CCDC_FLD_DIR_INPUT, CSL_CCDC_FLD_DIR_OUTPUT */
	Uint8 fieldDir;
	/** VD/HD Sync direction: CSL_CCDC_VDHD_DIR_INPUT, CSL_CCDC_VDHD_DIR_OUTPUT */
	Uint8 vdhdDir;
    /** Width of HD sync pulse when HD is set as an output 
		(note: CSL will write hdWidth-1 to register as per TRM)*/
	Uint16 hdWidth;
	/** Width of VD sync pulse when VD is set as an output
		(note: CSL will write vdWidth-1 to register as per TRM)*/
	Uint16 vdWidth;
}CSL_CcdcSyncModeConfig;


/** @brief CCDC Horizontal & Verical Pixel and Start Info structure.