csl_ccdc.h

TI达芬奇dm644x各硬件模块测试代码

/** @mainpage CCDC CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the CCDC module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given CCDC module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular CCDC Module. The CSL developer should use his discretion designing
 * new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification Document, Version 1.02
 *    -# CCDC_SPEC, CCDC Detailed Design Specification, Version 1.00.w.27 
 *
 */

/** @file csl_ccdc.h
 *
 * @brief    Header file for functional layer of CSL
 *
 * Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 * Modification 1
 *    - modified on: 10/19/2004
 *    - reason: Created the sources
 *
 * Modification 2
 *    - modified on: 04/08/2005
 *    - reason: Added several modifications based on DSC feedback
 *
 *
 * @date 19th Oct, 2004
 * @author Santosh Narayanan.
 *
 */
#ifndef _CSL_CCDC_H_
#define _CSL_CCDC_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <csl_error.h>
#include <csl_sysData.h>
#include <csl_types.h>
#include <cslr_ccdc.h>

/**************************************************************************\
* CCDC global macro declarations
\**************************************************************************/

/* the Field INSert and Fail NonReset macro */
#define CSL_FINSFNR(reg, PER_REG_FIELD, PER_FAIL_FIELD, val)                \
    ((reg) = (((reg) & ~CSL_##PER_REG_FIELD##_MASK)                          \
    | CSL_FMK(PER_REG_FIELD, val)) & ~CSL_FMK(PER_FAIL_FIELD, 1))

/** Constants for passing parameters to the CCDC HwSetup function.
 */

/** For indicating that the CCDC module is enabled    */
#define CSL_CCDC_ENABLE							(CSL_CCDC_PCR_ENABLE_ENABLE)
/** For indicating that the CCDC module is disabled   */
#define CSL_CCDC_DISABLE						(CSL_CCDC_PCR_ENABLE_DISABLE)

/** For indicating that the CCDC module is busy    */
#define CSL_CCDC_BUSY							(CSL_CCDC_PCR_BUSY_BUSY)
/** For indicating that the CCDC module is not busy    */
#define CSL_CCDC_NOT_BUSY						(CSL_CCDC_PCR_BUSY_NOTBUSY)

/** For indicating that the video port to SDRAM port path is enabled    */
#define CSL_CCDC_VP2SDR_ENABLE					(CSL_CCDC_SYN_MODE_VP2SDR_ENABLE)
/** For indicating that the video port to SDRAM port path is disabled    */
#define CSL_CCDC_VP2SDR_DISABLE					(CSL_CCDC_SYN_MODE_VP2SDR_DISABLE)

/** For indicating that the SDRAM output port is enabled    */
#define CSL_CCDC_SDRAM_OUT_ENABLE				(CSL_CCDC_SYN_MODE_WEN_ENABLE)
/** For indicating that the SDRAM output port is disabled    */
#define CSL_CCDC_SDRAM_OUT_DISABLE				(CSL_CCDC_SYN_MODE_WEN_DISABLE)

/** For indicating that the VD/HD is enabled    */
#define CSL_CCDC_VD_HD_ENABLE					(CSL_CCDC_SYN_MODE_VDHDEN_ENABLE)
/** For indicating that the VD/HD is disabled    */
#define CSL_CCDC_VD_HD_DISABLE					(CSL_CCDC_SYN_MODE_VDHDEN_DISABLE)

/** For indicating that the current field in interlaced mode is odd    */
#define CSL_CCDC_FLD_STATUS_ODDFIELD			(CSL_CCDC_SYN_MODE_FLDSTAT_ODDFIELD) 
/** For indicating that the current field in interlaced mode is even    */
#define CSL_CCDC_FLD_STATUS_EVENFIELD			(CSL_CCDC_SYN_MODE_FLDSTAT_EVENFIELD)

/** For indicating that the 3-tap low pass filter (anti-aliasing) is on    */
#define CSL_CCDC_LPF_ON							(CSL_CCDC_SYN_MODE_LPF_ON) 
/** For indicating that the 3-tap low pass filter (anti-aliasing) is off    */
#define CSL_CCDC_LPF_OFF						(CSL_CCDC_SYN_MODE_LPF_OFF)        

/** For indicating that the input to the CCDC is CCD raw data    */
#define CSL_CCDC_INPMOD_CCDRAW					(CSL_CCDC_SYN_MODE_INPMOD_CCDRAW)  
/** For indicating that the input to the CCDC is YCbCr 16-bit data    */
#define CSL_CCDC_INPMOD_YCBCR16					(CSL_CCDC_SYN_MODE_INPMOD_YCBCR16) 
/** For indicating that the input to the CCDC is YCbCr 8-bit data    */
#define CSL_CCDC_INPMOD_YCBCR8					(CSL_CCDC_SYN_MODE_INPMOD_YCBCR8)  

/** For indicating that the data should be put into SDRAM as 16 bits/pixel    */
#define CSL_CCDC_PACK8_16BITS_PIXEL				(CSL_CCDC_SYN_MODE_PACK8__16BITS_PIXEL)
/** For indicating that the data should be packed into SDRAM as 8 bits/pixel    */
#define CSL_CCDC_PACK8_8BITS_PIXEL				(CSL_CCDC_SYN_MODE_PACK8__8BITS_PIXEL) 

/** For indicating that the input width to the CCDC is 16 bits    */
#define CSL_CCDC_DATSIZ_16_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__16_BITS)
/** For indicating that the input width to the CCDC is 15 bits    */
#define CSL_CCDC_DATSIZ_15_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__15_BITS)
/** For indicating that the input width to the CCDC is 14 bits    */
#define CSL_CCDC_DATSIZ_14_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__14_BITS)
/** For indicating that the input width to the CCDC is 13 bits    */
#define CSL_CCDC_DATSIZ_13_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__13_BITS)
/** For indicating that the input width to the CCDC is 12 bits    */
#define CSL_CCDC_DATSIZ_12_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__12_BITS)
/** For indicating that the input width to the CCDC is 11 bits    */
#define CSL_CCDC_DATSIZ_11_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__11_BITS)
/** For indicating that the input width to the CCDC is 10 bits    */
#define CSL_CCDC_DATSIZ_10_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__10_BITS)
/** For indicating that the input width to the CCDC is 8 bits    */
#define CSL_CCDC_DATSIZ_8_BITS					(CSL_CCDC_SYN_MODE_DATSIZ__8_BITS) 

/** For indicating that the input to the CCDC is progressive    */
#define CSL_CCDC_FLDMODE_PROGRESSIVE			(CSL_CCDC_SYN_MODE_FLDMODE_NON_INTERLACED)
/** For indicating that the input to the CCDC is interlaced    */
#define CSL_CCDC_FLDMODE_INTERLACED				(CSL_CCDC_SYN_MODE_FLDMODE_INTERLACED)

/** For indicating that the CCD data polarity is normal    */
#define CSL_CCDC_DATAPOL_NORMAL					(CSL_CCDC_SYN_MODE_DATAPOL_NORMAL)
/** For indicating that the CCD data polarity is one's compliment    */
#define CSL_CCDC_DATAPOL_ONES_COMPLEMENT		(CSL_CCDC_SYN_MODE_DATAPOL_ONES_COMPLEMENT)

/** For indicating that the external write enable should not be used  */
#define CSL_CCDC_NO_EXTERNAL_WEN				(CSL_CCDC_SYN_MODE_EXWEN_NO_EXTERNAL_WEN)
/** For indicating that the external write enable should be used  */
#define CSL_CCDC_EXTERNAL_WEN					(CSL_CCDC_SYN_MODE_EXWEN_EXTERNAL_WEN)

/** For indicating that the field polarity is positive  */
#define CSL_CCDC_FLD_POL_POSITIVE				(CSL_CCDC_SYN_MODE_FLDPOL_POSITIVE)
/** For indicating that the field polarity is negative  */
#define CSL_CCDC_FLD_POL_NEGATIVE				(CSL_CCDC_SYN_MODE_FLDPOL_NEGATIVE)

/** For indicating that the HD polarity is positive  */
#define CSL_CCDC_HD_POL_POSITIVE				(CSL_CCDC_SYN_MODE_HDPOL_POSITIVE) 
/** For indicating that the field polarity is negative  */
#define CSL_CCDC_HD_POL_NEGATIVE				(CSL_CCDC_SYN_MODE_HDPOL_NEGATIVE) 

/** For indicating that the VD polarity is positive  */
#define CSL_CCDC_VD_POL_POSITIVE				(CSL_CCDC_SYN_MODE_VDPOL_POSITIVE) 
/** For indicating that the VD polarity is negative  */
#define CSL_CCDC_VD_POL_NEGATIVE				(CSL_CCDC_SYN_MODE_VDPOL_NEGATIVE) 

/** For indicating that the field direction is input  */
#define CSL_CCDC_FLD_DIR_INPUT					(CSL_CCDC_SYN_MODE_FLDOUT_INPUT)   
/** For indicating that the field direction is output  */
#define CSL_CCDC_FLD_DIR_OUTPUT					(CSL_CCDC_SYN_MODE_FLDOUT_OUTPUT)  

/** For indicating that the VD/HD direction is input  */
#define CSL_CCDC_VDHD_DIR_INPUT					(CSL_CCDC_SYN_MODE_VDHDOUT_INPUT)  
/** For indicating that the VD/HD direction is output  */
#define CSL_CCDC_VDHD_DIR_OUTPUT				(CSL_CCDC_SYN_MODE_VDHDOUT_OUTPUT) 

/** For indicating that the optical black clamping is enabled    */
#define CSL_CCDC_CLAMP_ENABLE					(CSL_CCDC_CLAMP_CLAMPEN_ENABLE) 
/** For indicating that the optical black clamping is disabled    */
#define CSL_CCDC_CLAMP_DISABLE					(CSL_CCDC_CLAMP_CLAMPEN_DISABLE)

/** For indicating that the alaw compression to sdram is enabled    */
#define CSL_CCDC_ALAW_ENABLE					(CSL_CCDC_ALAW_CCDTBL_ENABLE) 
/** For indicating that the alaw compression to sdram is disabled    */
#define CSL_CCDC_ALAW_DISABLE					(CSL_CCDC_ALAW_CCDTBL_DISABLE)

/** For indicating that the fault pixel correction is enabled    */
#define CSL_CCDC_FPC_ENABLED					(CSL_CCDC_FPC_FPCEN_ENABLED)     
/** For indicating that the fault pixel correction is disabled    */ 
#define CSL_CCDC_FPC_DISABLED					(CSL_CCDC_FPC_FPCEN_DISABLED)     

/** For indicating that the fault pixel correction was successful    */ 
#define CSL_CCDC_FPC_NOERROR					(CSL_CCDC_FPC_FPERR_NOERROR)      
/** For indicating that the fault pixel correction failed    */ 
#define CSL_CCDC_FPC_ERROR						(CSL_CCDC_FPC_FPERR_ERROR)        

/** For indicating that REC656 input mode is enabled   */ 
#define CSL_CCDC_REC656_ENABLE					(CSL_CCDC_REC656IF_R656ON_ENABLE) 
/** For indicating that REC656 input mode is disabled    */ 
#define CSL_CCDC_REC656_DISABLE					(CSL_CCDC_REC656IF_R656ON_DISABLE)

/** For indicating that REC656 FVH error correction is enabled   */ 
#define CSL_CCDC_REC656_ECCFVH_ENABLE			(CSL_CCDC_REC656IF_ECCFVH_ENABLE) 
/** For indicating that REC656 FVH error correction is disabled   */ 
#define	CSL_CCDC_REC656_ECCFVH_DISABLE			(CSL_CCDC_REC656IF_ECCFVH_DISABLE)

/** For indicating that REC656 input bit width is 8 bits   */ 
#define CSL_CCDC_REC656_8_BITS					(CSL_CCDC_CCDCFG_BW656__8_BITS)
/** For indicating that REC656 input bit width is 10 bits   */ 
#define CSL_CCDC_REC656_10_BITS					(CSL_CCDC_CCDCFG_BW656__10_BITS)

/** For indicating that latching function registers are latched on VSYNC   */ 
#define CSL_CCDC_LATCHED_ON_VSYNC				(CSL_CCDC_CCDCFG_VDLC_LATCHEDONVSYNC)
/** For indicating that latching function registers are not latched on VSYNC   */ 
#define CSL_CCDC_NOT_LATCHED_ON_VSYNC			(CSL_CCDC_CCDCFG_VDLC_NOTLATCHEDONVSYNC)

/** For indicating that the MSB of Chroma input signal is stored to SDRAM normally   */ 
#define CSL_CCDC_MSB_IN_NORMAL					(CSL_CCDC_CCDCFG_MSBINVI_NORMAL)
/** For indicating that the MSB of Chroma input signal is stored to SDRAM inverted   */
#define CSL_CCDC_MSB_IN_INVERTED				(CSL_CCDC_CCDCFG_MSBINVI_MSBINVERTED)

/** For indicating that the data stored to SDRAM is normal   */ 
#define CSL_CCDC_DONT_SWAPBYTES					(CSL_CCDC_CCDCFG_BSWD_NORMAL)    
/** For indicating that the data stored to SDRAM is byte swapped   */ 
#define CSL_CCDC_SWAPBYTES						(CSL_CCDC_CCDCFG_BSWD_SWAPBYTES) 

/** For indicating that the location of the Y signal when YCbCr 8 bit data is input is even   */ 
#define CSL_CCDC_Y8POS_EVENPIXEL				(CSL_CCDC_CCDCFG_Y8POS_EVENPIXEL)
/** For indicating that the location of the Y signal when YCbCr 8 bit data is input is odd   */
#define CSL_CCDC_Y8POS_ODDPIXEL					(CSL_CCDC_CCDCFG_Y8POS_ODDPIXEL) 

/** For indicating that the CCD valid signal occurs when the internal valid signal is logically ANDed to the WEN   */
#define CSL_CCDC_WENLOG_AND						(CSL_CCDC_CCDCFG_WENLOG_AND)     
/** For indicating that the CCD valid signal occurs when the internal valid signal is logically ORed to the WEN   */
#define CSL_CCDC_WENLOG_OR						(CSL_CCDC_CCDCFG_WENLOG_OR)      

/** For indicating that the FID signal is latched at VSYNC   */
#define CSL_CCDC_FID_LATCH_AT_VSYNC				(CSL_CCDC_CCDCFG_FIDMD_LATCH_AT_VSYNC)
/** For indicating that the FID signal is no latched at all   */
#define CSL_CCDC_FID_NO_LATCH					(CSL_CCDC_CCDCFG_FIDMD_NO_LATCH)
/** For indicating that the FID signal is latched at VD edge   */
#define CSL_CCDC_FID_LATCH_AT_VD_EDGE			(CSL_CCDC_CCDCFG_FIDMD_LATCH_AT_VD_EDGE)
/** For indicating that the FID signal is latched at phase of HD and VD  */
#define CSL_CCDC_FID_LATCH_ON_VD_HD_PHASE		(CSL_CCDC_CCDCFG_FIDMD_LATCH_ON_VD_HD_PHASE)

/** For indicating that the Y input and C input are not swapped   */
#define CSL_CCDC_NO_YCIN_SWAP					(CSL_CCDC_CCDCFG_YCINSWP_NO_YCIN_SWAP)
/** For indicating that the Y input and C input are swapped   */
#define CSL_CCDC_YCIN_SWAP						(CSL_CCDC_CCDCFG_YCINSWP_YCIN_SWAP)

/** For indicating that the video port output is enabled   */
#define CSL_CCDC_VIDEO_PORT_ENABLE				(CSL_CCDC_FMTCFG_VPEN_ENABLE) 
/** For indicating that the video port output is disabled   */
#define CSL_CCDC_VIDEO_PORT_DISABLE				(CSL_CCDC_FMTCFG_VPEN_DISABLE)

/** For indicating that the data reformatter is enabled   */
#define CSL_CCDC_FMT_ENABLE						(CSL_CCDC_FMTCFG_FMTEN_ON)    
/** For indicating that the data reformatter is disabled   */
#define	CSL_CCDC_FMT_DISABLE					(CSL_CCDC_FMTCFG_FMTEN_OFF)   

/** For indicating that the color pattern for the pixel is R/Ye   */
#define CSL_CCDC_R_YE							(0x00000000u)
/** For indicating that the color pattern for the pixel is Gr/Cy   */
#define CSL_CCDC_GR_CY							(0x00000001u)
/** For indicating that the color pattern for the pixel is Gb/Cy   */
#define CSL_CCDC_GB_G							(0x00000002u)
/** For indicating that the color pattern for the pixel is B/Mg   */
#define CSL_CCDC_B_MG							(0x00000003u)

/** For indicating that the number of pixels/lines for CLAMP is 1   */
#define CSL_CCDC_CLAMP_1						(0x00000000u)
/** For indicating that the number of pixels/lines for CLAMP is 2   */
#define CSL_CCDC_CLAMP_2						(0x00000001u)
/** For indicating that the number of pixels/lines for CLAMP is 4   */
#define CSL_CCDC_CLAMP_4						(0x00000002u)
/** For indicating that the number of pixels/lines for CLAMP is 8   */
#define CSL_CCDC_CLAMP_8						(0x00000003u)
/** For indicating that the number of pixels/lines for CLAMP is 16   */
#define CSL_CCDC_CLAMP_16						(0x00000004u)

/** For indicating that bits 15:6 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_15_6						(0x00000000u)
/** For indicating that bits 14:5 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_14_5						(0x00000001u)
/** For indicating that bits 13:4 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_13_4						(0x00000002u)
/** For indicating that bits 12:3 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_12_3						(0x00000003u)
/** For indicating that bits 11:2 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_11_2						(0x00000004u)
/** For indicating that bits 10:1 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_10_1						(0x00000005u)
/** For indicating that bits 9:0 will be used for ALAW or video port   */
#define CSL_CCDC_BITS_09_0						(0x00000006u)

/** For indicating that video port data ready frequency is 1/2   */
#define CSL_CCDC_VPIF_FRQ_ONE_HALF				(CSL_CCDC_FMTCFG_VPIF_FRQ_ONE_HALF)
/** For indicating that video port data ready frequency is 1/3   */