csl_venc.h

TI达芬奇dm644x各硬件模块测试代码

/** @mainpage VENC CSL 3.x
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to identify a set of common CSL APIs for
 * the VENC module across various devices. The CSL developer is expected to
 * refer to this document while designing APIs for these modules. Some of the
 * listed APIs may not be applicable to a given VENC module. While other cases
 * this list of APIs may not be sufficient to cover all the features of a
 * particular VENC Module. The CSL developer should use his discretion designing
 * new APIs or extending the existing ones to cover these.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *
 * @subsection References
 *    -# CSL-001-DES, CSL 3.x Design Specification DocumentVersion 1.02
 *    -# VENC_SPEC, VENC Module Specifications DocumentVersion 1.00.w.04  
 *
 */

/** @file csl_venc.h
 *
 * @brief    Header file for functional layer of CSL
 *
 * Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *
 * Modification 1
 *    - modified on: 10/3/2004
 *    - reason: Created the sources
 *
 *
 * @date 3rd October, 2004
 * @author Santosh Narayanan.
 *
 */
#ifndef _CSL_VENC_H_
#define _CSL_VENC_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <cslr.h>
#include <csl_error.h>
#include <csl_sysData.h>
#include <csl_types.h>
#include <cslr_venc.h>

/**************************************************************************\
* VENC global macro declarations
\**************************************************************************/

/** Constants for passing parameters to the VENC HwSetup function.
 */

/** Analog mode video */
#define CSL_VENC_ANALOG_MODE     (0)
/** Digital mode video */
#define CSL_VENC_DIGITAL_MODE     (1)
/** Mixed mode - both analog as well as digital output mode */
#define CSL_VENC_MIXED_MODE        (2)

/**************************************************************************\
* VENC global typedef declarations
\**************************************************************************/

/** @brief This object contains the reference to the instance of VENC opened
 *  using the @a CSL_vencOpen().
 *
 *  The pointer to this, is passed to all VENC CSL APIs.
 */
typedef struct CSL_VencObj {
	/** This is the mode which the CSL instance is opened     */
	CSL_OpenMode openMode;
	/** This is a unique identifier to the instance of VENC being
	 *  referred to by this object
	 */
	CSL_Uid uid;
	/** This is the variable that contains the current state of a
	 *  resource being shared by current instance of VENC with
     *  other peripherals
     */
	CSL_Xio xio;
	/** This is a pointer to the registers of the instance of VENC
     *  referred to by this object
     */
	CSL_VencRegsOvly regs;
	/** This is the instance of VENC being referred to by this object  */
	CSL_VencNum perNum;
}CSL_VencObj;

typedef struct CSL_VencObj *CSL_VencHandle;

/** @brief Analog Video Mode Basic Configuration structure
*
* All the basic fields needed for Analog Video mode configuration.
 */
typedef struct CSL_VencAnalogVideoConfig_{
       /** Scan mode: 0==> Interlace, 1==> Non-interlace*/
	Uint16 scanMode;   
	/** Non-interlace line number select */
	Uint16 itlcl;
	/** Non-standard interlace mode: 0==>Progressive, 1==>Interlace */
	Uint16 nsit;
	/** Blanking mode: 0==> Normal, 1==> Force blanking */
	Uint16 blankMode;
	/** Composite Output Enable: 0==> Fixed L level output, 
	      1==> Normal composite output */
	Uint16 compositeOut;
	/** DAC3 output select */
	Uint16 da3s;
	/** DAC2 output select */
	Uint16 da2s;
	/** DAC1 output select */
	Uint16 da1s;
	/** DAC0 output select */
	Uint16 da0s;
	/* Analog RGB matrix 0 */
	Uint16 analogRGBMat0;	
       /* Analog RGB matrix 0 */
	Uint16 analogRGBMat1;	
       /* Analog RGB matrix 2 */
	Uint16 analogRGBMat2;	
	/* Analog RGB matrix 3 */
	Uint16 analogRGBMat3;	
       /* Analog RGB matrix 4 */
	Uint16 analogRGBMat4;	
   
}CSL_VencAnalogVideoConfig;

/** @brief Analog Video Mode Extended Configuration structure
*
* Additional fields that are useful for Analog Video mode configuration.
 */
typedef struct CSL_VencAnalogVideoExtConfig_{
	/** Video Attribute Data Register 0 */
	Uint16 atr0;
	/** Video Attribute Data Register 1 */
	Uint16 atr1;
	/** Video Attribute Data Register 2 */
	Uint16 atr2;
	/** YOUT DC level */
	Uint16 ylvl;
	/** COUT DC level */
	Uint16 clvl;
	/** Sub-carrier inital phase value */
	Uint16 scsd;
	/* Closed caption default data */
	Uint16 cadf;
	/* Closed caption field select */
	Uint16 capf;
	/* Closed caption data 0 (Odd field) */
	Uint16 cado0;
	/* Closed caption data 1 (Odd field) */
	Uint16 cado1;
	/* Closed caption data 0 (Even field) */
	Uint16 cade0;
	/* Closed caption data 1 (Even field) */
	Uint16 cade1;
}CSL_VencAnalogVideoExtConfig;
	

/** @brief Video Processing structure.
*
* All fields needed for Video Processing for the analog mode.
 */
typedef struct CSL_VencVideoProcConfig_{

	/** Select C Prefilter: 0==>No filter, 1==> 1+1, 2==> 1+2+1 */
	Uint16 pfltc;
	/** Select Y Prefilter: 0==>No filter, 1==> 1+1, 2==> 1+2+1 */
	Uint16 pflty;
	/** Prefilter sampling frequency: 0==>ENC clock/2, 1==>ENC clock */
	Uint16 pfltr;
	/** Color bar type: 0==>75%, 1==>100% */
	Uint16 cbtyp;
	/** Color bar mode: 0==>Normal output, 1==> Color bar output */
	Uint16 cbmd;
	/** Input video attenuation control for RGB */
	Uint16 atrgb;
	/** Input video attenuation control for YCbCr */
	Uint16 atycc;
	/** Input video attenuation control for composite */
	Uint16 atcom;
	/** DAC x2 up-sampling enable */
	Uint16 daups;
	/** C signal up-sampling enable */
	Uint16 cups;
	/** Y signal up-sampling enable */
	Uint16 yups;
	
}CSL_VencVideoProcConfig;


/** @brief Horizontal & Vertical parameter configuration structure.
*
* All fields pertaining to horizontal and vertical sync, interval, start and delay.
 */
typedef struct CSL_VencHorzVertConfig_{

	/** Horizontal sync pulse width */
	Uint16 hspls;
	/** Vertical sync pulse width */
	Uint16 vspls;
	/** Horizontal interval */
	Uint16 hint;
	/** Horizontal valid data start position */
	Uint16 hstart;
	/** Horizontal data valid range */
	Uint16 hvalid;
	/** Vertical interval */
	Uint16 vint;
	/** Vertical valid data start position */
	Uint16 vstart;
	/** Vertical valid start position for even field */
	Uint16 vstarta;
	/** Vertical data valid range */
	Uint16 vvalid;
	/** Output delay of horz. sync signal */
	Uint16 hsdly;
	/** Output delay of vertical sync signal */
	Uint16 vsdly;
}CSL_VencHorzVertConfig;

/** @brief Digtial Video Config structure.
*
* All basic fields needed for digital mode video.
 */
typedef struct CSL_VencDigitalConfig_{

	/** Digital Video output Mode */
       Uint16  videoMode;
	/** VCLK output polarity */
	Uint16  vclkp;
	/** VCLK output enable */
	Uint16  vclke;
	/** VCLK pin output enable */
	Uint16  vclkz;
	/** Digital data output mode */
	Uint16  digDataOpMode;
	/** YOUT/COUT pin output interchange */
	Uint16  ycswap;
	/** YOUT/COUT pin output level */
	Uint16  ycol;
	/** YOUT/COUT pin output mode */
	Uint16  ycomd;
	/** YOUT/COUT pin direction */
	Uint16  ycdir;
	/** Digital RGB Matrix 0 */
	Uint16 digRGBMat0;
	/** Digital RGB Matrix 1 */
	Uint16 digRGBMat1;
	/** Digital RGB Matrix 2 */
	Uint16 digRGBMat2;
	/** Digital RGB Matrix 3 */
	Uint16 digRGBMat3;
	/** Digital RGB Matrix 4 */
	Uint16 digRGBMat4;

}CSL_VencDigitalConfig;

/** @brief YCC Control structure.
*
* All fields needed for YCC control.
 */
typedef struct CSL_VencYccCtlConfig_{

	/** YC output order */
	Uint16 ycp;
	/** REC656 mode */
	Uint16 r656;

}CSL_VencYccCtlConfig;

/** @brief  RGB Control structure.
*
* All fields needed for RGB control.
 */
typedef struct CSL_VencRgbCtlConfig_{

    /** RGB latch setting: 0==>Normal output, 1==> Latch mode */
	Uint16 rgblat;   
	/** Iron man type RGB output: 0==> Normal, 1==> Iron-man type */
	Uint16 ironm;
	/** Swap order of data in Iron Man mode: 0==>Normal, 1==> Data swap */
	Uint16 irswp;
	/** Iron Man 9 bit mode: 0==> 8 bit, 1==> 9 bit */
	Uint16 ir9;
	/** RGB LPF sampling frequency: 0==> ENC clock/2, 1==> ENC clock */
	Uint16 dfltr;
	/** RGB LPF Select: 0==>No filter, 1==> 1+2+1, 2==> 1+2+4+2+1 */
	Uint16 dflts;
	/** RGB output order (Line Id = 0) */
	Uint16 rgbef;
	/** RGB output order (Line Id = 1) */
	Uint16 rgbof;
	/** Upper Clip level for RGB output */
	Uint16 uclip;
	/** Offset level for RGB output */
	Uint16 ofst;

}CSL_VencRgbCtlConfig;

/** @brief  SYNC Control structure.
*
* All fields needed for SYNC control.
 */
typedef struct CSL_VencSyncCtlConfig_{

    /** OSD Vsync delay: 0==> Not delay, 1==>Delay 0.5H */
	Uint16 ovd;   
	/** External field detection mode */
	Uint16 exfmd;
	/** External field input inversion: 0==> non-inverse, 1==> inverse */
	Uint16 exfiv;
	/** External sync select: 0==> HSYNC/VSYNC pin, 1==> CCD sync signal */
	Uint16 exsync;
	/** External vertical sync input polarity: 0==>Active H, 1==> Active L */
	Uint16 exviv;
	/** External horx. sync input polarity: 0==>Active H, 1==> Active L */
	Uint16 exhiv;
	/** Composite signal output polarity: 0==> Active H, 1==> Active L */
	Uint16 csp;
	/** Composite signal output enable: 0==> Off, 1==> On */
	Uint16 cse;
	/** Output sync select: 0==>Normal, 1==> Sync pulse width proc. mode */
	Uint16 sysw;
	/** Vertical sync output signal: 0==> Vertical sync signal, 
	      1==> Composite sync signal */
	Uint16 vsyncs;
	/** Vertical sync output polarity: 0==> Active H, 1==> Active L */
	Uint16 vpl;
	/** Horizontal sync output polarity: 0==> Active H, 1==> Active L */
	Uint16 hpl;
	/** Vertical Sync ouput enable: 0==> Off, 1==> On */
	Uint16 syev;
	/** Horizontal Sync ouput enable: 0==> Off, 1==> On */
	Uint16 syeh;
	/** Horz/Vert sync I/O control */
	Uint16 sydir;

}CSL_VencSyncCtlConfig;

/** @brief  LINE Control structure.
*
* All fields needed for LINE control.
 */
typedef struct CSL_VencLineCtlConfig_{

	/** External Line Id signal polarity: 0==> Non-inverse, 1==>Inverse */
	Uint16 exidp;
	/** External Line Id signal input mode: 0==> Internal Id line,
	      1==> External Id line */
	Uint16 exide;
	/** Vertical data valid start position mode: 0==> Normal mode, 
	1==> Field mode */
	Uint16 vstf;
	/** Vertical culling line position */
	Uint16 vclid;
	/** Vertical culling counter reset mode: 0==> Reset to 0, 
	      1==> Reset to Random value */
	Uint16 vclrd;
	/** Digital output vertical culling: 0==> No culling, 1==>5/6 culling */
	Uint16 vcl56;
	/** Digital output field hold: 0==>Normal, 1==>Output hold */
	Uint16 hldf;
	/** Digital output line hold: 0==>Normal, 1==>Output hold */
	Uint16 hldl;
	/** Start line Id control in even field: 0==> Line Id=0, 1==> Line Id=1 */
	Uint16 linid;
	/** DCLK pattern switching by culling line Id: 0==>Off, 1==>On */
	Uint16 dckclp;
	/** DCLK polarity inversion by culling line Id: 0==>Off, 1==>On */
	Uint16 dckcli;
	/** RGB output order switching by culling line Id: 0==>Off, 1==>On */
	Uint16 rgbcl;
	/** Culling line Id toggle position (Odd field) */
	Uint16 clof;
	/** Culling line Id toggle position (even field) */
	Uint16 clef;
	/** Culling line Id inversion  interval */
	Uint16 culi;
	/** Horizontal valid culling mode: 0==>Normal, 1==> Horz. culling mode */
	Uint16 hcm;