csl_cachel1.c

TI达芬奇dm644x各硬件模块测试代码

        CACHE_L1Size oldSize ;

        oldSize = CACHE_setL1dSize(CACHE_L1_32KCACHE);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_setL1dSize, ".text:cslsys_section:cache");
CACHE_L1Size CACHE_setL1dSize (
    CACHE_L1Size                newSize
)
{
    Uint32 curSize;

    curSize = ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCFG;

    /* Critical Section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCFG = newSize;
    newSize = (CACHE_L1Size)((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCFG;
    asm(" rint");
    /* End critical section */

    return (CACHE_L1Size)(curSize);
}

/** ============================================================================
 *   @n@b CACHE_freezeL1d
 *
 *   @b Description
 *   @n Freezes L1D.
 *   @n As per the specification,
 *   @n a. The new freeze state is programmed in L1DCC.
 *   @n b. The old state is read from the L1DCC from the POPER field.
 *   @n    This latter read accomplishes 2 things, viz. Ensuring the new state
 *         is programmed as well as reading the old programmed value.
 *
 *   @b Arguments
 *   @n None
 *
 *   <b> Return Value </b>
 *   @n  Old Freeze State (CACHE_L1_Freeze)
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_L1_Freeze oldFreezeState ;

        oldFreezeState = CACHE_freezeL1d();
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_freezeL1d, ".text:cslsys_section:cache");
CACHE_L1_Freeze CACHE_freezeL1d (
    void
)
{
    Uint32 temp;

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCC =
                CSL_FMK(CACHE_L1DCC_OPER, CSL_CACHE_L1DCC_OPER_FREEZE);
    temp = CSL_FEXT(
                ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCC, CACHE_L1DCC_POPER);
    asm(" rint");
    /* end critical section */

    if (temp == CSL_CACHE_L1DCC_OPER_FREEZE)
        return CACHE_L1D_FREEZE;
    else
        return CACHE_L1D_NORMAL;
}

/** ============================================================================
 *   @n@b CACHE_unfreezeL1d
 *
 *   @b Description
 *   @n Unfreezes L1D.
 *   @n As per the specification,
 *   @n a. The normal state is programmed in L1DCC
 *   @n b. The old state is read from the L1DCC from the POPER field.
 *   @n    This latter read accomplishes 2 things, viz. Ensuring the new state
 *         is programmed as well as reading the old programmed value.
 *
 *   @b Arguments
 *   @n None
 *
 *   <b> Return Value </b>
 *   @n  Old Freeze State (CACHE_L1_Freeze)
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_L1_Freeze oldFreezeState ;

        oldFreezeState = CACHE_unfreezeL1d();
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_unfreezeL1d, ".text:cslsys_section:cache");
CACHE_L1_Freeze CACHE_unfreezeL1d (
    void
)
{
    Uint32 temp;

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCC =
                CSL_FMK(CACHE_L1DCC_OPER, CSL_CACHE_L1DCC_OPER_NORM);
    temp = CSL_FEXT(
                ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DCC, CACHE_L1DCC_POPER);
    asm(" rint");
    /* End critical section */

    if (temp == CSL_CACHE_L1DCC_OPER_NORM)
        return CACHE_L1D_NORMAL;
    else
        return CACHE_L1D_FREEZE;
}

/** ============================================================================
 *   @n@b CACHE_wbL1d
 *
 *   @b Description
 *   @n Writes back range specified in L1D.
 *   @n As per the specification,
 *   @n a. The start of the range that needs to be written back is programmed
 *         into L1DWBAR.
 *   @n b. The byte count is programmed in L1DWWC.
 *
 *   @b Arguments
 *   @verbatim
            blockPtr      Start address of range to be written back

            byteCnt       Number of bytes to be written back

            wait          Whether the call is blocking (and the extent of wait)
                          till the issue operation is completed or not.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbL1d((Uint32*)(0x1000), 200, CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbL1d, ".text:cslsys_section:cache");
void CACHE_wbL1d (
    void           *blockPtr,
    Uint32          byteCnt,
    CACHE_Wait      wait
)
{
    CACHE_waitInternal();

    /* Critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DWBAR = (Uint32)blockPtr;
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DWWC =((byteCnt+3)>>2);
    /* End critical section */

    _CSL_cachebusyState = CACHE_WAIT_L1DWB;
    _CSL_cacheEmifState =
        (CACHE_emifState)(CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr)
        + CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
    asm(" rint");

    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_invL1d
 *
 *   @b Description
 *   @n Invalidates range specified in L1D.
 *   @n As per the specification,
 *   @n a. The start of the range that needs to be invalidated is written
 *         into L1DIBAR.
 *   @n b. The byte count is programmed in L1DIWC.
 *
 *   @b Arguments
 *   @verbatim
            blockPtr      Start address of range to be invalidated

            byteCnt       Number of bytes to be invalidated

            wait          Whether the call is blocking (and the extent of wait)
                          till the issue operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_invL1d ((Uint32*)(0x1000), 200, CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_invL1d, ".text:cslsys_section:cache");
void CACHE_invL1d (
    void            *blockPtr,
    Uint32           byteCnt,
    CACHE_Wait       wait
)
{
    CACHE_waitInternal();

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DIBAR = (Uint32)blockPtr;
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DIWC  = ((byteCnt+3)>>2);
    _CSL_cachebusyState = CACHE_WAIT_L1DINV;
    asm(" rint");
    /* End critical section */

    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_wbInvL1d
 *
 *   @b Description
 *   @n Writeback invalidates range specified in L1D.
 *   @n As per the specification,
 *   @n a. The start of the range that needs to be writeback invalidated is
 *         programmed into L1DWIBAR.
 *   @n b. The byte count is programmed in L1DWIWC.
 *
 *   @b Arguments
 *   @verbatim
            blockPtr      Start address of range to be written back invalidated

            byteCnt       Number of bytes to be written back invalidated

            wait          Whether the call is blocking (and the extent of wait)
                          till the issue operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbInvL1d ((Uint32*)(0x1000),200,CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbInvL1d, ".text:cslsys_section:cache");
void CACHE_wbInvL1d (
    void              *blockPtr,
    Uint32             byteCnt,
    CACHE_Wait         wait
)
{
    CACHE_waitInternal();

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DWIBAR = (Uint32)blockPtr;
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DWIWC = ((byteCnt+3)>>2);
    _CSL_cachebusyState = CACHE_WAIT_L1DWBINV;
    _CSL_cacheEmifState =
        (CACHE_emifState)(CSL_CACHE_EMIF_ISRANGE((Uint32)blockPtr)
        + CSL_CACHE_EMIF_ISEMIFBRANGE((Uint32)blockPtr));
    asm(" rint");
    /* End critical section */

    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_wbAllL1d
 *
 *   @b Description
 *   @n Writeback All of L1D.
 *   @n As per the specification,
 *   @n a. The L1DWB is programmed.
 *
 *   @b Arguments
 *   @verbatim
            wait          Whether the call is blocking (and the extent of wait)
                          till the issue operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbAllL1d (CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbAllL1d, ".text:cslsys_section:cache");
void CACHE_wbAllL1d (
    CACHE_Wait        wait
)
{
    CACHE_waitInternal();

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DWB = 1;
    _CSL_cachebusyState = CACHE_WAIT_L1DWBALL;
    _CSL_cacheEmifState = CACHE_EMIF_AB;
    asm(" rint");
    /* End critical section */

    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_invAllL1d
 *
 *   @b Description
 *   @n Invalidates All of L1D.
 *   @n As per the specification,
 *   @n a. The L1DINV is programmed.
 *
 *   @b Arguments
 *   @verbatim
            wait          Whether the call is blocking (and the extent of wait)
                          till the issue operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_invAllL1d (CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_invAllL1d, ".text:cslsys_section:cache");
void CACHE_invAllL1d (
    CACHE_Wait         wait
)
{
    CACHE_waitInternal();

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DINV = 1;
    /* End critical section */
    _CSL_cachebusyState = CACHE_WAIT_L1DINVALL;
    asm(" rint");

    if (wait)
        _CACHE_wait(wait);
}

/** ============================================================================
 *   @n@b CACHE_wbInvAllL1d
 *
 *   @b Description
 *   @n Writeback invalidates All of L1D.
 *   @n As per the specification,
 *   @n a. The L1DWBINV is programmed.
 *
 *   @b Arguments
 *   @verbatim
            wait          Whether the call is blocking (and the extent of wait)
                          till the issue operation is completed.
                          Whether the function must exit on completion/or not.
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_wbInvAllL1d (CACHE_NOWAIT);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_wbInvAllL1d, ".text:cslsys_section:cache");
void CACHE_wbInvAllL1d (
    CACHE_Wait           wait
)
{
    CACHE_waitInternal();

    /* critical section */
    asm(" dint");
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->L1DWBINV = 1;
    /* critical section */
    _CSL_cachebusyState = CACHE_WAIT_L1DWBINVALL;
    _CSL_cacheEmifState = CACHE_EMIF_AB;
    asm(" rint");

    if (wait)
        _CACHE_wait(wait);
}