csl_cacheenable.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** \file csl_cacheEnable.c
 *
 *  \brief This file defines the functions in the Cache driver.
 *
 *  Date 22th March 2004
 *  Author Jamon Bowen
 *
 *  Description
 *  - The functions in this driver contian all of the necessary
 *       functionallity the configure the (if avalible) L2, L1D, and L1P Cache.
 *  Last Modified: 22th March 2004
 *
 *  Modifications 1:
 *  - Jamon Bowen
 *  - Created
 *  - Date: 23th March 2004
 *
 *  Modifications 2:
 *  - Ruchika Kharwar
 *  - Created
 *  - Date: 21st June 2004
 *  - Removed global variable, Cache (redundant), Register Layer modified to be
 *    CSL 3.x Register layer as
 *    specified in the scope.
 */

#include <csl_cache.h>
#include "_csl_cache.h"

/** ============================================================================
 *   @n@b CACHE_enableCaching
 *
 *   @b Description
 *   @n Enables caching for the specified memory range.
 *
 *   @b Arguments
 *   @verbatim
            mar        EMIF range
     @endverbatim
 *
 *   <b> Return Value </b>
 *   @n  None
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  Caching for the specified memory range is enabled
 *
 *   @b Modifies
 *   @n MAR register
 *
 *   @b Example
 *   @verbatim
        ...
        CACHE_enableCaching (CACHE_EMIFB_CE00);
        ...
     @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CACHE_enableCaching, ".text:cslsys_section:cache");
void CACHE_enableCaching (
    CE_MAR                 mar
)
{
    ((CSL_CacheRegsOvly)CSL_CACHE_REGS)->MAR[mar] = 1;
}