📄 csl_tsc.asm
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.global _CSL_ctimerStart
.sect ".text:cslsys_section:ctimer"
_CSL_ctimerStart:
MVC A4, TSCL ; Initiate CPU Timer by writing to TSCL
B B3 ; Branch Return - Wait 1 cycle to allow
; TSCL to go to one prior to reading
MVC TSCL, B4 ; Read TSCL - Should = 0x000000001 if
; timer was not already running
MVC TSCH, B5 ; Read TSCH - Should = 0x000000000 if
; timer was not already running
|| CMPEQ 1, B4, B0 ; Compare TSCL to 1
|| MVK -1, A1 ; A1 = -1 => CSL_ESYS_FAIL
; (Generic CSL Failure)
[B0] CMPEQ 0, B5, B0 ; Compare TSCH to 0 if TSCL == 0x1
|| MV B4, A4 ; Copy TSCL to Return Register
; (should be 1)
[!B0] MV A1, A4 ; If TSCH != 0 or TSCH != 1 then
; Return (CSL_ESYS_FAIL)
NOP ; Fill Delay Slot of Branch
.global _CSL_tscEnable
.sect ".text:cslsys_section:tsc"
_CSL_tscEnable:
BNOP B3, 4 ;
MVC A4, TSCL ; Initiate CPU Timer by writing to TSCL
.global _CSL_ctimerRead
.sect ".text:cslsys_section:ctimer"
_CSL_ctimerRead:
BNOP B3, 1 ; Branch Return Pointer
DINT ; Disable Interrupts to insure TSCH is read
; after TSCL w/o interrupt inbetween
|| MVC TSCL, B0 ; Read TSCL
RINT ; Reenable Interrupts after TSCH is read
|| MVC TSCH, B1 ; Read TSCH
|| STW B0, *A4 ; Store TSCL to *timerLow
STW B1, *B4 ; Store TSCL to *timerHigh
MVK 1, A4 ; Set Return to 1, CSL_SOK - (Success)
.global _CSL_tscRead
.sect ".text:cslsys_section:tsc"
_CSL_tscRead:
BNOP B3, 2 ; Branch Return Pointer
MVC TSCL, B0 ; Read TSCL
MVC TSCH, B1 ; Read TSCH
|| MV B0, A4
MV B1, A5
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