csl_edcgethwstatus.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 
/** @file csl_edcGetHwStatus.c
 *
 *  @brief    File for functional layer of CSL API @a CSL_edcGetHwStatus()
 *
 *  Description
 *    - The @a CSL_edcGetHwStatus() function definition & it's associated functions
 *
 *  @date 9 July, 2004
 *  @author Chad Courtney
 */

#include <csl_edc.h>

#pragma CODE_SECTION (CSL_edcGetHwStatus, ".text:csl_section:edc")

/** @brief Gets the requested HW Status of the specified memory.
 */
CSL_Status  CSL_edcGetHwStatus(
	/** Specificies what memory EDC status is to be obtained for
     */
	CSL_EdcMem              edcMem,
    /** The query to this API which indicates the status
     *  to be returned
	 */
    CSL_EdcHwStatusQuery                  query,
    /** Placeholder to return the status. @a void* casted */
    void                                      *response
	){

	CSL_Status status = CSL_SOK;

	switch(query) {
	case CSL_EDC_QUERY_ENABLESTAT:		/* Query Enable/Disable status */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
			*((CSL_EdcEnableStatus*)response) =(CSL_EdcEnableStatus)
												(
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT, EDC_L1PEDSTAT_LOGICEN) |			
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT, EDC_L1PEDSTAT_LOGICDIS) << 1 |
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT, EDC_L1PEDSTAT_SUSP) << 2
												); // Ruchika - typecasting to get rid of warning 
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((CSL_EdcEnableStatus*)response) =	(CSL_EdcEnableStatus)
												(
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_LOGICEN) |
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_LOGICDIS) << 1 |
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L1PEDSTAT_SUSP) << 2
												); // Ruchika - typecasting to get rid of warning 
												
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;
		
  	case CSL_EDC_QUERY_ERRORSTAT:		/* Query error status */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
			*((CSL_EdcErrorStatus*)response) =  (CSL_EdcErrorStatus)	
												(
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT, EDC_L1PEDSTAT_IERR) << 1 |
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT, EDC_L1PEDSTAT_DMAERR) << 2
												);// Ruchika - typecasting to get rid of warning 
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((CSL_EdcErrorStatus*)response) =	(CSL_EdcErrorStatus)	
												(
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_DERR) |
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_IERR) << 1 |
												CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_DMAERR) << 2
												);// Ruchika - typecasting to get rid of warning 
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
  		break;
  		
  	case CSL_EDC_QUERY_NERRSTAT:		/* Query number of bit error status (L2 only) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
    		status = CSL_ESYS_INVQUERY;	/* Invalid Query - L1P does not have NERR */
		}else if(edcMem == CSL_EDC_L2){ /* EDC HW Status query applies to L2 */
			*((CSL_EdcNumErrors*)response) = (CSL_EdcNumErrors)	(CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_NERR));
											// Ruchika - typecasting to get rid of warning 
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
  		break;
  		
  	case CSL_EDC_QUERY_BITPOS:			/* Query bit position of error (L2 only) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
    		status = CSL_ESYS_INVQUERY;	/* Invalid Query - L1P does not provide bit position */
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((Uint32*)response)	=	CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, EDC_L2EDSTAT_BITPOS);
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;
		
  	case CSL_EDC_QUERY_ALLSTAT:			/* Query all status (returns EDSTAT register) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
			*((Uint32*)response)	=	//CSL_FEXTR(((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT, 31, 0); // Ruchika - not necessary
										((CSL_EdcRegs*)CSL_EDC_REGS)->L1PEDSTAT;
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((Uint32*)response)	=	//CSL_FEXTR(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT, 31, 0);
										((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDSTAT;
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;

  	case CSL_EDC_QUERY_PAGE0:			/* Query Page 0 enables (L2 only) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
    		status = CSL_ESYS_INVQUERY;	/* Invalid Query - L1P does not have Page Enables */
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((Uint32*)response)	=	//CSL_FEXTR(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDEN0, 31, 0); // Ruchika 
									   ((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDEN0;
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;
		
  	case CSL_EDC_QUERY_PAGE1:			/* Query Page 1 enables (L2 only) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
    		status = CSL_ESYS_INVQUERY;	/* Invalid Query - L1P does not have Page Enables */
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((Uint32*)response)	=	//CSL_FEXTR(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDEN1, 31, 0); //Ruchika
										((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDEN1;
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;
		
  	case CSL_EDC_QUERY_CE_CNT:			/* Query correctable parity error count (L2 only) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
    		status = CSL_ESYS_INVQUERY;	/* Invalid Query - L1P does not provide error count */
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((Uint32*)response)	=	CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDCPEC, EDC_L2EDCPEC_CNT);
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;
		
  	case CSL_EDC_QUERY_NCE_CNT: 		/* Query non-correctable parity error count (L2 only) */
		if(edcMem == CSL_EDC_L1P){		/* EDC HW Status query applies to L1P */
    		status = CSL_ESYS_INVQUERY;	/* Invalid Query - L1P does not provide error count */
		}else if(edcMem == CSL_EDC_L2){	/* EDC HW Status query applies to L2 */
			*((Uint32*)response)	=	CSL_FEXT(((CSL_EdcRegs*)CSL_EDC_REGS)->L2EDNPEC, EDC_L2EDNPEC_CNT);
		}else{							/* Incorrect Memory Type given for EDC Status Query */
    		status = CSL_ESYS_INVQUERY;
    	}
		break;

    default:
    	status = CSL_ESYS_INVQUERY ;

	}
	return status;
}