csl_edma.h

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */
/** @mainpage EDMA
 *
 * @section Introduction
 *
 * @subsection xxx Purpose and Scope
 * The purpose of this document is to detail the  CSL APIs for the
 * EDMA Module.
 *
 * @subsection aaa Terms and Abbreviations
 *   -# CSL:  Chip Support Library
 *   -# API:  Application Programmer Interface
 *   -# EDMA: Enhanced Direct Memory Access
 *
 * @subsection References
 *    -# CSL 3.x Technical Requirements Specifications Version 0.5, dated
 *       May 14th, 2003
 *    -# EDMA Channel Controller Specification (Revision 0.25)
 *    -# EDMA Transfer Controller Specification (Revision 0.14)
 *
 * @subsection Assumptions
 *     The abbreviations EDMA, edma and Edma have been used throughout this
 *     document to refer to Enhanced Direct Memory Access.
 */

/** @file csl_edma.h
 *
 *   @path $(CSLPATH)\\armedma\\src
 *
 *    @brief    Header file for functional layer CSL of EDMA
 *
 *  Description
 *    - The different enumerations, structure definitions
 *      and function declarations
 *  Last Modified : 29th June 2004
 */
 
/* =============================================================================
 *  Revision History
 *  ===============
 *  10-Aug-2005  brn      Updated for doxygen documentation and butification
 * =============================================================================
 */
 
#ifndef _CSL_EDMA_H_
#define _CSL_EDMA_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <csl.h>
#include <socEdma.h>
#include <soc64plus.h>
#include <cslr_edmacc.h>


/**
@defgroup CSL_EDMA_API EDMA
*/
/**
@defgroup CSL_EDMA_DATASTRUCT  EDMA Data Structures
@ingroup CSL_EDMA_API
*/
/**
@defgroup CSL_EDMA_SYMBOL  EDMA Symbols Defined
@ingroup CSL_EDMA_API
*/
/**
@defgroup CSL_EDMA_ENUM  EDMA Enumerated Data Types
@ingroup CSL_EDMA_API
*/

/**
@defgroup CSL_EDMA_FUNCTION  EDMA Functions
@ingroup CSL_EDMA_API
*/
/**
@defgroup CSL_EDMA_FUNCTION_MODULE  EDMA Module Functions
@ingroup CSL_EDMA_FUNCTION
*/
/**
@defgroup CSL_EDMA_FUNCTION_SHADOW EDMA Region Functions
@ingroup CSL_EDMA_FUNCTION
*/
/**
@defgroup CSL_EDMA_FUNCTION_CHANNEL EDMA Channel Functions
@ingroup CSL_EDMA_FUNCTION
*/
/**
@defgroup CSL_EDMA_FUNCTION_MODULE_INTERNAL  EDMA Module Internal Functions
@ingroup CSL_EDMA_FUNCTION_MODULE
*/
/**
@defgroup CSL_EDMA_FUNCTION_SHADOW_INTERNAL  EDMA Region Internal Functions
@ingroup CSL_EDMA_FUNCTION_SHADOW
*/
/**
@defgroup CSL_EDMA_FUNCTION_CHANNEL_INTERNAL  EDMA Channel Internal Functions
@ingroup CSL_EDMA_FUNCTION_CHANNEL
*/
/** @addtogroup CSL_EDMA_SYMBOL
* @{ */
#define CSL_EDMA_LINK_NULL                 0xFFFF
/**< Link to a Null Param entry */
#define CSL_EDMA_LINK_DEFAULT              0xFFFF
/**< Link to a Null Param entry */
#define CSL_EDMA_SYNC_A                    0
/**< A sycnhronized transfer  */
#define CSL_EDMA_SYNC_AB                   1
/**< AB sycnhronized transfer */
#define CSL_EDMA_SYNC_ARRAY                CSL_EDMA_SYNC_A
/**< Array/A sycnhronized transfer */
#define CSL_EDMA_SYNC_FRAME                CSL_EDMA_SYNC_AB
/**< Frame/AB sycnhronized transfer */
#define CSL_EDMA_TCC_NORMAL                    0
/**< Normal Completion */
#define CSL_EDMA_TCC_EARLY                     1
/**< Early  Completion */
#define CSL_EDMA_FIFOWIDTH_NONE                0
/**< Only for ease  */
#define CSL_EDMA_FIFOWIDTH_8BIT                0
/**< 8 bit FIFO Width */
#define CSL_EDMA_FIFOWIDTH_16BIT               1
/**< 16 bit FIFO Width */
#define CSL_EDMA_FIFOWIDTH_32BIT               2
/**< 32 bit FIFO Width */
#define CSL_EDMA_FIFOWIDTH_64BIT               3
/**< 64 bit FIFO Width */
#define CSL_EDMA_FIFOWIDTH_128BIT              4
/**< 128 bit FIFO Width */
#define CSL_EDMA_FIFOWIDTH_256BIT              5
/**< 256 bit FIFO Width */
#define CSL_EDMA_ADDRMODE_INCR                 0
/**< Address Mode is incremental */
#define CSL_EDMA_ADDRMODE_FIFO                 1
/**< Address Mode is such it wraps around after reaching FIFO width */


/* Bitwise OR of the below symbols are used for setting the Memory attributes
   These are defined only if the Memory Protection feature exists */
#if CSL_EDMA_MEMPROTECT

#define CSL_EDMA_MEMACCESS_UX              0x0001
/**< User Execute permission */
#define CSL_EDMA_MEMACCESS_UW              0x0002
/**< User Write permission */
#define CSL_EDMA_MEMACCESS_UR              0x0004
/**< User Read permission */
#define CSL_EDMA_MEMACCESS_SX              0x0008
/**< Supervisor Execute permission */
#define CSL_EDMA_MEMACCESS_SW              0x0010
/**< Supervisor Write permission */
#define CSL_EDMA_MEMACCESS_SR              0x0020
/**< Supervisor Read permission */
#define CSL_EDMA_MEMACCESS_EMU             0x0040
/**< Emulation security permission */
#define CSL_EDMA_MEMACCESS_NS              0x0080
/**< Non secure Access permission */
#define CSL_EDMA_MEMACCESS_EXT             0x0200
/**< External Allowed ID. VBus requests with PrivID >= '6' are permitted if 
 *   access type is allowed
 */

#define CSL_EDMA_MEMACCESS_AID0        0x0400
/**< Allowed ID '0' */
#define CSL_EDMA_MEMACCESS_AID1        0x0800
/**< Allowed ID '1' */
#define CSL_EDMA_MEMACCESS_AID2        0x1000
/**< Allowed ID '2' */
#define CSL_EDMA_MEMACCESS_AID3        0x2000
/**< Allowed ID '3' */
#define CSL_EDMA_MEMACCESS_AID4        0x4000
/**< Allowed ID '4' */
#define CSL_EDMA_MEMACCESS_AID5        0x8000
/**< Allowed ID '5' */

#endif
#define CSL_EDMA_TRIGWORD_NONE         7
/**< No trigger word. Useful while doing setup for EDMA channels */
#define CSL_EDMA_TRIGWORD_DEFAULT      7
/**< Last trigger word in a QDMA parameter entry */


/** Used for creating the options entry in the parameter ram */
#define CSL_EDMA_OPT_MAKE(itccEn,tccEn,itcintEn,tcintEn,tcc,tccMode,fwid,stat, \
    syncDim,dam,sam) (Uint32)(\
     CSL_FMKR(23,23,itccEn) \
    |CSL_FMKR(22,22,tccEn) \
    |CSL_FMKR(21,21,itcintEn) \
    |CSL_FMKR(20,20,tcintEn) \
    |CSL_FMKR(17,12,tcc) \
    |CSL_FMKR(11,11,tccMode) \
    |CSL_FMKR(10,8,fwid) \
    |CSL_FMKR(3,3,stat) \
    |CSL_FMKR(2,2,syncDim) \
    |CSL_FMKR(1,1,dam) \
    |CSL_FMKR(0,0,sam))
/** Used for creating the A,B Count entry in the parameter ram */
#define CSL_EDMA_CNT_MAKE(aCnt,bCnt) \
(Uint32)(\
     CSL_FMK(EDMACC_A_B_CNT_ACNT,aCnt) \
    |CSL_FMK(EDMACC_A_B_CNT_BCNT,bCnt)\
    )
/** Used for creating the link and B count reload entry in the parameter ram */
#define CSL_EDMA_LINKBCNTRLD_MAKE(link,bCntRld) \
(Uint32)(\
     CSL_FMK(EDMACC_LINK_BCNTRLD_LINK,link) \
    |CSL_FMK(EDMACC_LINK_BCNTRLD_BCNTRLD,bCntRld)\
    )
/** Used for creating the B index entry in the parameter ram */
#define CSL_EDMA_BIDX_MAKE(src,dst) \
(Uint32)(\
     CSL_FMK(EDMACC_SRC_DST_BIDX_DSTBIDX,dst) \
    |CSL_FMK(EDMACC_SRC_DST_BIDX_SRCBIDX,src)\
    )

/** Used for creating the C index entry in the parameter ram */
#define CSL_EDMA_CIDX_MAKE(src,dst) \
(Uint32)(\
     CSL_FMK(EDMACC_SRC_DST_CIDX_DSTCIDX,dst) \
    |CSL_FMK(EDMACC_SRC_DST_CIDX_SRCCIDX,src)\
    )
/**
@}
*/


/**
@addtogroup CSL_EDMA_ENUM
@{
*/
/** @brief Enumeration for VBusM priority
*
* This is used for Setting up the Queue Priority level
*/
typedef enum {
    CSL_EDMA_VBUSM_PRI0 = 0,         /**< VBusM priority level 0 */
    CSL_EDMA_VBUSM_PRI1 = 1,         /**< VBusM priority level 1 */
    CSL_EDMA_VBUSM_PRI2 = 2,         /**< VBusM priority level 2 */
    CSL_EDMA_VBUSM_PRI3 = 3,         /**< VBusM priority level 3 */
    CSL_EDMA_VBUSM_PRI4 = 4,         /**< VBusM priority level 4 */
    CSL_EDMA_VBUSM_PRI5 = 5,         /**< VBusM priority level 5 */
    CSL_EDMA_VBUSM_PRI6 = 6,         /**< VBusM priority level 6 */
    CSL_EDMA_VBUSM_PRI7 = 7          /**< VBusM priority level 7 */
}CSL_EdmaEventQueuePri;

/** @brief Enumeration for EDMA Queue Thresholds
*
* This is used for Setting up the Queue thresholds
*/
typedef enum {
    CSL_EDMA_QUETHRESH_0 = 0,        /**< EDMA Queue Threshold 0 */
    CSL_EDMA_QUETHRESH_1 = 1,        /**< EDMA Queue Threshold 1 */
    CSL_EDMA_QUETHRESH_2 = 2,        /**< EDMA Queue Threshold 2 */
    CSL_EDMA_QUETHRESH_3 = 3,        /**< EDMA Queue Threshold 3 */
    CSL_EDMA_QUETHRESH_4 = 4,        /**< EDMA Queue Threshold 4 */
    CSL_EDMA_QUETHRESH_5 = 5,        /**< EDMA Queue Threshold 5 */
    CSL_EDMA_QUETHRESH_6 = 6,        /**< EDMA Queue Threshold 6 */
    CSL_EDMA_QUETHRESH_7 = 7,        /**< EDMA Queue Threshold 7 */
    CSL_EDMA_QUETHRESH_8 = 8,        /**< EDMA Queue Threshold 8 */
    CSL_EDMA_QUETHRESH_9 = 9,        /**< EDMA Queue Threshold 9 */
    CSL_EDMA_QUETHRESH_10 = 10,      /**< EDMA Queue Threshold 10 */
    CSL_EDMA_QUETHRESH_11 = 11,      /**< EDMA Queue Threshold 11 */
    CSL_EDMA_QUETHRESH_12 = 12,      /**< EDMA Queue Threshold 12 */
    CSL_EDMA_QUETHRESH_13 = 13,      /**< EDMA Queue Threshold 13 */
    CSL_EDMA_QUETHRESH_14 = 14,      /**< EDMA Queue Threshold 14 */
    CSL_EDMA_QUETHRESH_15 = 15,      /**< EDMA Queue Threshold 15 */
    CSL_EDMA_QUETHRESH_16 = 16,      /**< EDMA Queue Threshold 15 */
    CSL_EDMA_QUETHRESH_DISABLE = 17  /**< EDMA Queue Threshold Disable Errors */
}CSL_EdmaEventQueueThr;

/** @brief MODULE Level Commands
*
*
*/
typedef enum {
#if CSL_EDMA_MEMPROTECT
    CSL_EDMA_CMD_MEMPROTECT_SET,       /**< (Arg: @a #CSL_EdmaCmdQueryRegion*)
                                        *   Programmation of MPPAG,MPPA[0-7]
                                        *   attributes
                                        */
#endif
    CSL_EDMA_CMD_DMAREGION_ENABLE,     /**< (Arg: @a #CSL_EdmaCmdDmaRegion*  )
                                        *   Programmation of DRAE,DRAEH region
                                        *   Enable attributes
                                        */
    CSL_EDMA_CMD_DMAREGION_DISABLE,    /**< (Arg: @a #CSL_EdmaCmdDmaRegion*  )
                                        *   Programmation of DRAE,DRAEH region
                                        *   Disable attributes
                                        */
    CSL_EDMA_CMD_QDMAREGION_ENABLE,    /**< (Arg: @a #CSL_EdmaCmdQueryRegion*)
                                        *   Programmation of QRAE region Enable
                                        *   attributes
                                        */
    CSL_EDMA_CMD_QDMAREGION_DISABLE,   /**< (Arg: @a #CSL_EdmaCmdQueryRegion*)
                                        *   Programmation of QRAE region Disable
                                        *   attributes
                                        */
    CSL_EDMA_CMD_QUEPRIORITY_SET,      /**< (Arg: @a #CSL_EdmaCmdQuePriority*)
                                        *   Programmation of QUEPRI register
                                        *   with the specified priority
                                        */
    CSL_EDMA_CMD_QUETHRESHOLD_SET,     /**< (Arg: @a #CSL_EdmaCmdQueThr* )
                                        *   Programmation of QUE Threshold
                                        *   levels
                                        */
    CSL_EDMA_CMD_QUETC_MAP,            /**< (Arg: @a #CSL_EdmaCmdQueTc* )
                                        *   Programmation of QUE to TC Mapping
                                        */
    CSL_EDMA_CMD_ERROR_EVAL,           /**< (Arg: #None)Programmation of Error
                                        *   Evaluation
                                        */
    CSL_EDMA_CMD_INTERRUPT_CLEAR,      /**< (Arg: @a #CSL_BitMask32* )Clears
                                        *   specified (Bitmask)pending interrupt
                                        *   at Module Level
                                        */
    CSL_EDMA_CMD_INTERRUPT_ENABLE,     /**< (Arg: @a #CSL_BitMask32* )Enables
                                        *   specified interrupts(BitMask) at
                                        *   Module Level
                                        */
    CSL_EDMA_CMD_INTERRUPT_DISABLE,    /**< (Arg: @a #CSL_BitMask32* )Disables
                                        *   specified interrupts(BitMask) at
                                        *   Module Level
                                        */
    CSL_EDMA_CMD_INTERRUPT_EVAL        /**< (Arg: #None )Interrupt Evaluation
                                        *   asserted for the Module
                                        */
}CSL_EdmaHwControlCmd;

/** @brief MODULE Level Queries
*
*
*/
typedef enum {
    CSL_EDMA_QUERY_REVISION,            /**< (Arg: @a #Uint32*)Returns the
                                         *   revision of the module
                                         */
#if CSL_EDMA_MEMPROTECT
    CSL_EDMA_QUERY_MEMFAULT,            /**< (Arg: @a #CSL_EdmaMemFaultStatus*)
                                         *   Return the Memory fault attributes
                                         *  \n Also Clears the Memory Fault
                                         */
    CSL_EDMA_QUERY_MEMPROTECT,          /**< (Arg: @a #CSL_EdmaCmdQueryRegion*)
                                         *   Return memory attribute of the
                                         *   specified region */
#endif
    CSL_EDMA_QUERY_CTRLERROR,           /**< (Arg: @a #CSL_EdmaccStatus*)Return
                                         *   Controller Error and \n Also Clears
                                         *   the Controller Error
                                         */
    CSL_EDMA_QUERY_INTERRUPT_PENDSTATUS,/**< (Arg: @a #CSL_BitMask32*)Return
                                         *   pend status of specified interrupt
                                         */

    CSL_EDMA_QUERY_INTERRUPT_MISSED     /**< (Arg: @a #CSL_BitMask32*)Returns
                                         *   Miss Status of all interrupts \n
                                         *   Also clears the missed status
                                         */
}CSL_EdmaHwStatusQuery;

/** @brief SHADOW REGION Level Commands
*
*
*/