_csl_pscpddsppwronoff.c

TI达芬奇dm644x各硬件模块测试代码

#include <csl_pscAux.h>
#include <cslr_sys.h>
#include <soc.h>

#pragma CODE_SECTION (CSL_pscPdDspPwrOnOff, ".text:csl_section:psc");

CSL_Status  CSL_pscPdDspPwrOnOff(
    CSL_PscHandle           hPsc,
    CSL_PscPdState          pdState
	){

  CSL_PscRegsOvly pscRegs = hPsc->regs;
  CSL_SysRegsOvly sysRegs = (CSL_SysRegsOvly) CSL_SYS_1_REGS;
  
  /* If DSP PD is already in the desired state (on or off) then just return CSL_SOK */  
  if( pdState == CSL_FEXT( pscRegs->PDSTAT[CSL_PSC_PD_DSP], PSC_PDSTAT_STATE) ){
    return (CSL_SOK);  
  }
  
  /* Wait for PTSTAT.GOSTAT1 to clear to 0x0 before initiating a new transition */  
//Law:Comment out since DSP PD seems to be in a 0x11 state after reset.  while( ( CSL_FEXT(pscRegs->PTSTAT, PSC_PTSTAT_GOSTAT1) )  ==  CSL_PSC_PTSTAT_GOSTAT_TRANSITIONING ){/* wait */;}

  /*Set PDCTL1.NEXT to 0x1 */
  CSL_FINS(pscRegs->PDCTL[CSL_PSC_PD_DSP], PSC_PDCTL_NEXT, pdState);   
  
  if( pdState == CSL_PSC_PD_STATE_ON ){
    /* Set MDCTL39.NEXT to 0x3 for DSP ENABLE State */
    CSL_FINS(pscRegs->MDCTL[CSL_PSC_MD_DSP],   PSC_MDCTL_NEXT, CSL_PSC_MD_STATE_ENABLE); 
    /* Set MDCTL40.NEXT to 0x3 for IMCOP ENABLE State */
    CSL_FINS(pscRegs->MDCTL[CSL_PSC_MD_IMCOP], PSC_MDCTL_NEXT, CSL_PSC_MD_STATE_ENABLE); 
  }else{
    /* Set MDCTL39.NEXT to 0x2 for DSP DISABLE State */
    CSL_FINS(pscRegs->MDCTL[CSL_PSC_MD_DSP], PSC_MDCTL_NEXT, CSL_PSC_MD_STATE_DISABLE);   
    /* Set MDCTL40.NEXT to 0x3 for IMCOP DISABLE State */
    CSL_FINS(pscRegs->MDCTL[CSL_PSC_MD_DSP], PSC_MDCTL_NEXT, CSL_PSC_MD_STATE_DISABLE);   
  }
        
  /* Set PTCMD.GO1 to 0x1 to initiate the state transition */
  CSL_FINS(pscRegs->PTCMD, PSC_PTCMD_GO1, CSL_PSC_PTCMD_GO_GO );                        

  /* Wait for EPCPR.EPC1 to change to 0x1 */
  while( ( CSL_FEXT(pscRegs->EPCPR, PSC_EPCPR_EPC1) )  !=  CSL_PSC_EPCPR_EPC_EPC_REQUEST ){/* Note: Wait time will be 2 DSP/6 clock cycles.  For power-off, you must execute IDLE instruction on DSP or wait is forever. */;}

  /* Clear EPC interrupt */ 
  CSL_FINS(pscRegs->EPCCR, PSC_EPCCR_EPC1, CSL_PSC_EPCCR_EPC_CLEAR_EPC );   
  /* This command assumes that power is available at VDDDSP an no intervention is required */

  if( pdState == CSL_PSC_PD_STATE_ON ){
    /* Set CHIPSHRTSW.DSPPWRON to 0x1 */
    CSL_FINS(sysRegs->CHIP_SHORT_SWITCH, SYS_CHIP_SHORT_SWITCH_DSPPWRON, CSL_SYS_CHIP_SHORT_SWITCH_DSPPWRON_ON );
    /* Set PDCTL1.EPCGOOD to 0x1 */
    CSL_FINS(pscRegs->PDCTL[1], PSC_PDCTL_EPCGOOD, CSL_PSC_PDCTL_EPCGOOD_EXT_PWR_ON );                                          
  }else{
    /* Set CHIPSHRTSW.DSPPWRON to 0x0 */
    CSL_FINS(sysRegs->CHIP_SHORT_SWITCH, SYS_CHIP_SHORT_SWITCH_DSPPWRON, CSL_SYS_CHIP_SHORT_SWITCH_DSPPWRON_OFF );
    /* Set PDCTL1.EPCGOOD to 0x0 */
    CSL_FINS(pscRegs->PDCTL[1], PSC_PDCTL_EPCGOOD, CSL_PSC_PDCTL_EPCGOOD_EXT_PWR_OFF );                                          
  }
         
  /* Wait for PTSTAT.GOSTAT1 to clear to 0x0 */
  while( ( CSL_FEXT(pscRegs->PTSTAT, PSC_PTSTAT_GOSTAT1) )  == CSL_PSC_PTSTAT_GOSTAT_TRANSITIONING ){/* wait */;}
  
  return (CSL_SOK);
}