csl_uartgethwsetup.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */
 
/** @file csl_uartGetHwSetup.c
 *  
 *  @brief    File for functional layer of CSL API @a CSL_uartGetHwSetup()
 *
 *  Path: \\(CSLPATH)\\ipmodules\\uart\\src
 *
 *  Description
 *    - The @a CSL_uartGetHwSetup() function definition & it's associated
 *      functions
 *  @date 6 May, 2004
 *  @author Pratheesh Gangadhar
 */
 
/* =============================================================================
 *  Revision History
 *  ===============
 *  07-Sep-2004 brn Updated for the new CSL architecture
 *  11-Oct-2004 brn Updated with the code review comments.
 * =============================================================================
*/ 

#include <csl_uart.h>

/** ============================================================================
 *   @n@b CSL_uartGetHwSetup
 *
 *   @b Description
 *   @n Gets the output status of UART 
 *
 *   @b Arguments
 *   @verbatim
        hUart            Handle to the UART instance
        setup            Pointer to the hard ware setup 
 *   @endverbatim
 *
 *   <b> Return Value </b>  Uint32
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *    @n Returns the status of UART read register
 *
 *   @b Modifies
 *   @n  None
 *
 *   @b Example
 *   @verbatim
        CSL_UartHandle     hUart;
        Uint32             stat;
        CSL_UartHwSetup   *setup
        ...
        stat = CSL_uartGetHwSetup (hUart, setup);
        ...
     @endverbatim
 * ===========================================================================
 */
#pragma CODE_SECTION (CSL_uartGetHwSetup, ".text:csl_section:uart");
CSL_Status CSL_uartGetHwSetup ( 
    CSL_UartHandle    hUart,
    CSL_UartHwSetup   *setup 
) 
{
    CSL_UartRegsOvly uartRegs = hUart->regs; 
    Uint32 tempIntEn;
    Uint16 divisor;
    
    CSL_UartLineConfig tmpsetupLine;
    CSL_UartFifoConfig tmpsetupFifo;
    
    if (hUart == NULL ) {
        return CSL_ESYS_BADHANDLE;
    }   
    
    if (setup == NULL) {
        return CSL_ESYS_INVPARAMS;
    }
    
    /* To access divisor latches of the baud generator */     
    CSL_FINSR(uartRegs->LCR, 7, 7, 1);
    divisor = CSL_FEXT (uartRegs->DLL, UART_DLL_DLL)
              | CSL_FEXT (uartRegs->DLH, UART_DLH_DLH) << 8;
              
    /* Pratheesh G 05/06/2004
     * I think about getting rid of moduleClock field by using
     * constant instead */         
    setup->setupBaud.baudrate = setup->setupBaud.moduleClock/(16 * divisor);
    
    /* Restore the LCR DLAB state */
    CSL_FINSR(uartRegs->LCR, 7, 7, 0);    
    
    tmpsetupLine.charLen = (CSL_UartCharLen)
                            CSL_FEXT (uartRegs->LCR, UART_LCR_WLS);
    tmpsetupLine.numStopBits = (CSL_UartNumStop)
                                CSL_FEXT (uartRegs->LCR, UART_LCR_STB);
    tmpsetupLine.parityCtrl = 0;
    
    if (uartRegs->LCR & CSL_FMK(UART_LCR_PEN, 1))
      tmpsetupLine.parityCtrl |= CSL_UART_PARITY_ENABLE;
      
    if (uartRegs->LCR & CSL_FMK(UART_LCR_EPS, 1))
      tmpsetupLine.parityCtrl |= CSL_UART_PARITY_EVEN;  
      
    if (uartRegs->LCR & CSL_FMK(UART_LCR_SP, 1))
      tmpsetupLine.parityCtrl |= CSL_UART_STICKPARITY_ENABLE;    
      
    setup->setupLine = tmpsetupLine; 
                                
    setup->fifoEnable = (CSL_UartFifoCtrl)
                         CSL_FEXT (uartRegs->FCR, UART_FCR_FIFOEN);
    
    tmpsetupFifo.trigLevel = (CSL_UartRxFifoTrigLevel)
                              CSL_FEXT (uartRegs->FCR, UART_FCR_RXFIFTL);
    tmpsetupFifo.dmaMode = (CSL_UartDmaCtrl)
                            CSL_FEXT (uartRegs->FCR, UART_FCR_DMAMODE1);
    
    setup->setupFifo = tmpsetupFifo; 
    
    if ( CSL_FEXT (uartRegs->MCR, UART_MCR_AFE)) {
        if (CSL_FEXT (uartRegs->MCR, UART_MCR_RTS)) {
            setup->flowControl = CSL_UART_AUTO_CTS_RTS;  
        } 
        else {
            setup->flowControl = CSL_UART_AUTO_CTS;  
        }
    
    } 
    else {
        setup->flowControl = CSL_UART_AUTOFLOW_DISABLE;   
    }
       
    CSL_FINSR (uartRegs->LCR, 7, 7, 0);
    
    tempIntEn = 0;
    
    if (CSL_FEXT (uartRegs->IER, UART_IER_EDSSI))
        tempIntEn |= CSL_UART_INTR_MODEMSTAT;
        
    if (CSL_FEXT (uartRegs->IER, UART_IER_ELSI))
        tempIntEn |= CSL_UART_INTR_RXLINESTAT;  
        
    if (CSL_FEXT (uartRegs->IER, UART_IER_ETBEI))
        tempIntEn |= CSL_UART_INTR_THR_EMPTY;    
        
    if (CSL_FEXT (uartRegs->IER, UART_IER_ERBI))
        tempIntEn |= CSL_UART_INTR_RDA_CTI;  
          
    setup->interruptEnable = tempIntEn;
       
    setup->loopEnable = (CSL_UartLoopCtrl)
                         CSL_FEXT (uartRegs->MCR, UART_MCR_LOOP);
                                    
    setup->emuConfig = (CSL_UartEmuCtrl)
                        CSL_FEXT (uartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_FREE);
    return CSL_SOK;
}