csl_uarthwsetup.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */

/** @file csl_uartHwSetup.c
 *  
 *  @brief    File for functional layer of CSL API @a CSL_uartHwSetup()
 *
 *  Path: \\(CSLPATH)\\ipmodules\\uart\\src
 *
 *  Description
 *   - The @a CSL_uartHwSetup() function definition & it's associated functions
 *
 *  @date 30 April, 2004
 *  @author Pratheesh Gangadhar
 */
 
/* =============================================================================
 *  Revision History
 *  ===============
 *  07-Sep-2004 brn Updated for the new CSL architecture
 *  11-Oct-2004 brn Updated with the code review comments.
 *  19-Jan-2005 brn Updated DLL and DLH registers setup with the TI suggessions
 * =============================================================================
*/ 
 
#include <csl_uart.h>

/** ============================================================================
 *   @n@b   CSL_uartHwSetup
 *
 *   @b Description
 *   @n This function initializes the device registers with the appropriate values
 *  provided through the HwSetup Data structure. This function needs to be 
 *  called only if the HwSetup Structure was not previously passed through the 
 *  Open call. After the Setup is completed, the serial device is ready for 
 *  data transfer. For information passed through the HwSetup Data structure 
 *  refer @a CSL_UartHwSetup.
 *   @b Arguments
 *
 *   @verbatim
            hUart           Handle to the UARTS instance

            setup           Pointer to hardware setup structure
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Hardware setup successful
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *   @li                    CSL_ESYS_INVPARAMS  - Hardware structure is not
 *                                                properly initialized
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The specified instance will be setup according to value passed
 *
 *   @b Modifies
 *   @n Hardware registers for the specified instance
 *
 *  <b> Usage Constraints: 
 *  Both @a CSL_uartInit() and @a CSL_uartOpen() must be called
 *  successfully in that order before this function can be called. The user
 *  has to allocate space for & fill in the main setup structure appropriately
 *  before calling this function
 *
 * @b Example:
 * @verbatim
     CSL_UartHandle hUart;
     CSL_UartHwSetup hwSetup = CSL_UART_HWSETUP_DEFAULTS;
     CSL_uartHwSetup(hUart, &hwSetup);
  @endverbatim
 *
 * ============================================================================
 */
#pragma CODE_SECTION (CSL_uartHwSetup, ".text:csl_section:uart");
CSL_Status CSL_uartHwSetup ( 
    CSL_UartHandle      hUart,
    CSL_UartHwSetup     *setup 
) 
{
 
    CSL_UartRegsOvly uartRegs = hUart->regs; 
    Uint16           divisor;
    CSL_UartBaudConfig tmpsetupBaud = setup->setupBaud;
    CSL_UartLineConfig tmpsetupLine = setup->setupLine;
    CSL_UartFifoConfig tmpsetupFifo = setup->setupFifo;
    
    if (hUart == NULL ) {
        return CSL_ESYS_BADHANDLE;
    }   
    
    if (setup == NULL) {
        return CSL_ESYS_INVPARAMS;
    }
    
    divisor = tmpsetupBaud.moduleClock/(16 * tmpsetupBaud.baudrate);
    
    /* To access divisor latches of the baud generator */     
    CSL_FINSR(uartRegs->LCR, 7, 7, 1);
    
    /* Changed the DLL and DLH setup with the reflection to cslr_uart.h changes
     * which was suggested by TI
     */  
    uartRegs->DLL = (divisor & 0xFF);
    uartRegs->DLH = ((divisor & 0xFF00) >> 8);
    
    /* Restore the LCR DLAB state */
    CSL_FINSR(uartRegs->LCR, 7, 7, 0);    
     
    uartRegs->LCR = (CSL_FMK (UART_LCR_WLS, tmpsetupLine.charLen)  
                    |CSL_FMK (UART_LCR_STB, tmpsetupLine.numStopBits)
                    |(tmpsetupLine.parityCtrl << 3) );
                    
    if (setup->fifoEnable != 0) {
      uartRegs->FCR = (CSL_FMK (UART_FCR_FIFOEN, CSL_UART_FCR_FIFOEN_ENABLE) 
                      |CSL_FMK (UART_FCR_RXFIFTL, tmpsetupFifo.trigLevel)
                      |CSL_FMK (UART_FCR_DMAMODE1, tmpsetupFifo.dmaMode) 
                      |CSL_FMK (UART_FCR_TXCLR, CSL_UART_FCR_TXCLR_CLR)
                      |CSL_FMK (UART_FCR_RXCLR, CSL_UART_FCR_RXCLR_CLR) ); 
    }
    else {
          
        uartRegs->FCR = (CSL_FMK (UART_FCR_FIFOEN, CSL_UART_FCR_FIFOEN_DISABLE) 
                        |CSL_FMK (UART_FCR_RXFIFTL, tmpsetupFifo.trigLevel)
                        |CSL_FMK (UART_FCR_DMAMODE1, tmpsetupFifo.dmaMode) 
                        |CSL_FMK (UART_FCR_TXCLR, CSL_UART_FCR_TXCLR_CLR)
                        |CSL_FMK (UART_FCR_RXCLR, CSL_UART_FCR_RXCLR_CLR) );
    }
         
    switch (setup->flowControl) {
        case CSL_UART_AUTOFLOW_DISABLE:
            CSL_FINS (uartRegs->MCR, UART_MCR_AFE, CSL_UART_MCR_AFE_DISABLE);  
            CSL_FINS (uartRegs->MCR, UART_MCR_RTS, CSL_UART_MCR_RTS_DISABLE); 
            break;
          
        case CSL_UART_AUTO_CTS_RTS:  
            CSL_FINS (uartRegs->MCR, UART_MCR_AFE, CSL_UART_MCR_AFE_ENABLE);  
            CSL_FINS (uartRegs->MCR, UART_MCR_RTS, CSL_UART_MCR_RTS_ENABLE);  
            break;
          
        case CSL_UART_AUTO_CTS:  
            CSL_FINS (uartRegs->MCR, UART_MCR_AFE, CSL_UART_MCR_AFE_ENABLE);
            break;
    }
        
    CSL_FINSR (uartRegs->LCR, 7, 7, 0);
    uartRegs->IER = setup->interruptEnable;      
       
    CSL_FINS (uartRegs->MCR, UART_MCR_LOOP, setup->loopEnable);
    CSL_FINS (uartRegs->PWREMU_MGMT, UART_PWREMU_MGMT_FREE, setup->emuConfig);
    
    return CSL_SOK;
}