csl_vlynqhwsetup.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** @file  csl_vlynqHwSetup.c
 *
 *    @brief File for functional layer of CSL API @a CSL_vlynqHwSetup()
 *
 *  Description
 *    - The @a CSL_vlynqHwSetup() function definition,currently just a place
 *     holder
 *
 */

#include <csl_vlynq.h>

/** Sets up the VLYNQ module using the values passed in through the
 * setup structure. The setup structure consists of pointers to
 * substructures. If these pointers are set to @a NULL, then the setup
 * corresponding to that sub-structure is not done.
 *
 * @return returns the status of the setup operation
 */
#pragma CODE_SECTION (CSL_vlynqHwSetup, ".text:csl_section:vlynq");
CSL_Status  CSL_vlynqHwSetup(
    /** pointer to the object that holds reference to the
     * instance of VLYNQ requested after the call */
    CSL_VlynqHandle                        hVlynq,
    /** pointer to setup structure which contains the
     * information to program VLYNQ to a useful state */
    CSL_VlynqHwSetup                       *setup
)
{
    Uint32 temp;
    CSL_VlynqRegsOvly regsPtr = hVlynq->regs;

    if ( (setup == NULL) && (setup->localHwSetup == NULL) ) {
        /* If setup is NULL, indicate an error */
        /* If localHwSetup is NULL, indicate an error */
        return CSL_ESYS_INVPARAMS;
    }

    /* Fill up the fields in Control register as per the localHwSetup
     *  structure for local VLYNQ */

    temp = regsPtr->CTRL;

    /* disable pmen */
    CSL_FINS(temp,
             VLYNQ_CTRL_PMEN,
             setup->localHwSetup->pMen );

    /* enable serial clock pull-up disable */
    CSL_FINS(temp,
             VLYNQ_CTRL_SCLKXPUDIS,
             setup->localHwSetup->sclkPuDis);

    /* set default RTM rxsampleval = 0x03 */
    /* Razak: Need to check whether this write will work out..
     *  b'caz, this needs simlutaneous write 1 to 'rtmvalidwr' */
    CSL_FINS(temp,
            VLYNQ_CTRL_RXSAMPELVAL,
            (CSL_VlynqRtmSampleVal)setup->localHwSetup->rxSampleVal);

    /* set RTM write as invlaid */
    CSL_FINS(temp,
             VLYNQ_CTRL_RTMVALIDWR,
             setup->localHwSetup->rtmValidWr);

    /* disable RTM */
    CSL_FINS(temp,
             VLYNQ_CTRL_RTMENABLE,
             setup->localHwSetup->rtmEnable);

    /* txfastpath = slow */
    CSL_FINS(temp,
             VLYNQ_CTRL_TXFASTPATH,
             setup->localHwSetup->txFastPath);

    /* serial clock divider val = 1*/
    CSL_FINS(temp,
             VLYNQ_CTRL_CLKDIV,
             (CSL_VlynqSclkDiv)setup->localHwSetup->sclkDiv);

    /* serial clock direction as external = 0  */
    CSL_FINS(temp,
             VLYNQ_CTRL_CLKDIR,
             (CSL_VlynqClkDir)setup->localHwSetup->sclkDir);

    /* intlocal = 0 */
    CSL_FINS(temp,
             VLYNQ_CTRL_INTLOCAL,
             setup->localHwSetup->intLocal);

    /* disable status interrupts */
    CSL_FINS(temp,
             VLYNQ_CTRL_INTENABLE,
             setup->localHwSetup->intEnable);

    /* int2cfg:Use INTPTR to point local config register */
    CSL_FINS(temp,
             VLYNQ_CTRL_INT2CFG,
             setup->localHwSetup->int2cfg);

    /* enable address optimization disable */
    CSL_FINS(temp,
             VLYNQ_CTRL_AOPTDISABLE,
             setup->localHwSetup->aOptDisable);

    /* disable internal loop */
    CSL_FINS(temp,
             VLYNQ_CTRL_ILOOP,
             setup->localHwSetup->iLoop);

    /* de-assert the RESET */
    CSL_FINS(temp,
             VLYNQ_CTRL_RESET,
             setup->localHwSetup->reset);

    /* fill up the CTRL Control register from the structure */
    regsPtr->CTRL  = temp;

    /* set INTPTR to point config register */
    /* Commented=> Razak:
    CSL_FINS(regsPtr->INTPTR,
             VLYNQ_INTPTR_INTPTR,
             setup->localHwSetup->intPtr); */
    CSL_FINS(regsPtr->INTPTR,
             VLYNQ_INTPTR_INTPTR,
             (Uint32)((CSL_VlynqAdrPtr)setup->localHwSetup->intPtr));

    /* Tx Address Map */
    /* Commented=> Razak:
    CSL_FINS(regsPtr->XAM,
             VLYNQ_XAM_TXADRMAP,
             setup->localHwSetup->txAdrMap); */
    CSL_FINS(regsPtr->XAM,
             VLYNQ_XAM_TXADRMAP,
             (Uint32)((CSL_VlynqAdrPtr)setup->localHwSetup->txAdrMap));

    /* Rx Addres Map Size1 */
    CSL_FINS(regsPtr->RAMS1,
             VLYNQ_RAMS1_RXADRSIZE1,
             setup->localHwSetup->rxAdrSize1);
    /* Rx Address Map Offset1 */
    /* Commented=> Razak
    CSL_FINS(regsPtr->RAMO1,
             VLYNQ_RAMO1_RXADROFFSET1,
             setup->localHwSetup->rxAdrOffset1); */
    CSL_FINS(regsPtr->RAMO1,
             VLYNQ_RAMO1_RXADROFFSET1,
             (Uint32)setup->localHwSetup->rxAdrOffset1);

    /* Rx Addres Map Size2 */
    CSL_FINS(regsPtr->RAMS2,
             VLYNQ_RAMS2_RXADRSIZE2,
             setup->localHwSetup->rxAdrSize2);
    /* Rx Address Map Offset2 */
    /* Commented=> Razak
    CSL_FINS(regsPtr->RAMO2,
             VLYNQ_RAMO2_RXADROFFSET2,
             setup->localHwSetup->rxAdrOffset2); */
    CSL_FINS(regsPtr->RAMO2,
             VLYNQ_RAMO2_RXADROFFSET2,
             (Uint32)setup->localHwSetup->rxAdrOffset2);

    /* Rx Addres Map Size3 */
    CSL_FINS(regsPtr->RAMS3,
             VLYNQ_RAMS3_RXADRSIZE3,
             setup->localHwSetup->rxAdrSize3);

    /* Rx Address Map Offset3 */
    /* Commented=> Razak
    CSL_FINS(regsPtr->RAMO3,
             VLYNQ_RAMO3_RXADROFFSET3,
             setup->localHwSetup->rxAdrOffset3); */
    CSL_FINS(regsPtr->RAMO3,
             VLYNQ_RAMO3_RXADROFFSET3,
             (Uint32)setup->localHwSetup->rxAdrOffset3);

    /* Rx Addres Map Size4 */
    CSL_FINS(regsPtr->RAMS4,
             VLYNQ_RAMS4_RXADRSIZE4,
             setup->localHwSetup->rxAdrSize4);

    /** Rx Address Map Offset4 */
    /* Commented=> Razak
    CSL_FINS(regsPtr->RAMO4,
             VLYNQ_RAMO4_RXADROFFSET4,
             setup->localHwSetup->rxAdrOffset4); */
    CSL_FINS(regsPtr->RAMO4,
             VLYNQ_RAMO4_RXADROFFSET4,
             (Uint32)setup->localHwSetup->rxAdrOffset4);

    /** Fill up the fields in Config register as per the remoteHwSetup
     *  structure for remote VLYNQ if remote Setup structure in non-NULL */
    if (setup->remoteHwSetup != NULL) {
        temp = regsPtr->RCTRL;

        /* disable pmen */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_PMEN,
                 setup->remoteHwSetup->pMen );

        /* enable serial clock pull-up disable */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_SCLKXPUDIS,
                 setup->remoteHwSetup->sclkPuDis);

        /* set default RTM rxsampleval = 0x03 */
        /* Razak: This needs to be checked, as it needs simultaneous write
         * write to 'rtmvalidwr' bit */
        CSL_FINS(temp,
                VLYNQ_RCTRL_RXSAMPELVAL,
                (CSL_VlynqRtmSampleVal)setup->remoteHwSetup->rxSampleVal);

        /* set RTM write as invlaid */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_RTMVALIDWR,
                 setup->remoteHwSetup->rtmValidWr);

        /* disable RTM */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_RTMENABLE,
                 setup->remoteHwSetup->rtmEnable);

        /* txfastpath = slow */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_TXFASTPATH,
                 setup->remoteHwSetup->txFastPath);

        /* serial clock divider val = 1*/
        CSL_FINS(temp,
                 VLYNQ_RCTRL_CLKDIV,
                 (CSL_VlynqSclkDiv)setup->remoteHwSetup->sclkDiv);

        /* serial clock direction as external = 0  */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_CLKDIR,
                 (CSL_VlynqClkDir)setup->remoteHwSetup->sclkDir);

        /* intlocal = 0 */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_INTLOCAL,
                 setup->remoteHwSetup->intLocal);

        /* disable status interrupts */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_INTENABLE,
                 setup->remoteHwSetup->intEnable);

        /* int2cfg:Use INTPTR to point local config register */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_INT2CFG,
                 setup->remoteHwSetup->int2cfg);

        /* enable address optimization disable */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_AOPTDISABLE,
                 setup->remoteHwSetup->aOptDisable);

        /* disable internal loop */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_ILOOP,
                 setup->remoteHwSetup->iLoop);

        /* de-assert the RESET */
        CSL_FINS(temp,
                 VLYNQ_RCTRL_RESET,
                 setup->remoteHwSetup->reset);

        /* fill up the CTRL Control register from the structure */
        regsPtr->RCTRL = temp;

        /* set INTPTR to point config register */
        /* Commented=> Razak
        CSL_FINS(regsPtr->RINTPTR,
                 VLYNQ_RINTPTR_INTPTR,
                 setup->remoteHwSetup->intPtr); */
        CSL_FINS(regsPtr->RINTPTR,
                 VLYNQ_RINTPTR_INTPTR,
                 (Uint32)setup->remoteHwSetup->intPtr);

        /** Tx Address Map */
        /* Commented=> Razak
        CSL_FINS(regsPtr->RXAM,
                 VLYNQ_RXAM_TXADRMAP,
                 setup->remoteHwSetup->txAdrMap); */
        CSL_FINS(regsPtr->RXAM,
                 VLYNQ_RXAM_TXADRMAP,
                 (Uint32)setup->remoteHwSetup->txAdrMap);

        /** Rx Addres Map Size1 */
        CSL_FINS(regsPtr->RRAMS1,
                 VLYNQ_RRAMS1_RXADRSIZE1,
                 setup->remoteHwSetup->rxAdrSize1);
        /** Rx Address Map Offset1 */
        /* Commented=> Razak
        CSL_FINS(regsPtr->RRAMO1,
                 VLYNQ_RRAMO1_RXADROFFSET1,
                 setup->remoteHwSetup->rxAdrOffset1); */
        CSL_FINS(regsPtr->RRAMO1,
                 VLYNQ_RRAMO1_RXADROFFSET1,
                 (Uint32)setup->remoteHwSetup->rxAdrOffset1);

        /** Rx Addres Map Size2 */
        CSL_FINS(regsPtr->RRAMS2,
                 VLYNQ_RRAMS2_RXADRSIZE2,
                 setup->remoteHwSetup->rxAdrSize2);

        /** Rx Address Map Offset2 */
        /* Commented=> Razak
        CSL_FINS(regsPtr->RRAMO2,
                 VLYNQ_RRAMO2_RXADROFFSET2,
                 setup->remoteHwSetup->rxAdrOffset2); */
        CSL_FINS(regsPtr->RRAMO2,
                 VLYNQ_RRAMO2_RXADROFFSET2,
                 (Uint32)setup->remoteHwSetup->rxAdrOffset2);

        /** Rx Addres Map Size3 */
        CSL_FINS(regsPtr->RRAMS3,
                 VLYNQ_RRAMS3_RXADRSIZE3,
                 setup->remoteHwSetup->rxAdrSize3);

        /** Rx Address Map Offset3 */
        /* Commented=> Razak
        CSL_FINS(regsPtr->RRAMO3,
                 VLYNQ_RRAMO3_RXADROFFSET3,
                 setup->remoteHwSetup->rxAdrOffset3); */
        CSL_FINS(regsPtr->RRAMO3,
                 VLYNQ_RRAMO3_RXADROFFSET3,
                 (Uint32)setup->remoteHwSetup->rxAdrOffset3);

        /** Rx Addres Map Size4 */
        CSL_FINS(regsPtr->RRAMS4,
                 VLYNQ_RRAMS4_RXADRSIZE4,
                 setup->remoteHwSetup->rxAdrSize4);

        /** Rx Address Map Offset4 */
        /* Commented=> Razak
        CSL_FINS(regsPtr->RRAMO4,
                 VLYNQ_RRAMO4_RXADROFFSET4,
                 setup->remoteHwSetup->rxAdrOffset4); */
        CSL_FINS(regsPtr->RRAMO4,
                 VLYNQ_RRAMO4_RXADROFFSET4,
                 (Uint32)setup->remoteHwSetup->rxAdrOffset4);
    }

    return CSL_SOK;

}