csl_vlynqhwcontrol.c

TI达芬奇dm644x各硬件模块测试代码

             *  given address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrOffset3Set (hVlynq, (CSL_VlynqAdrPtr)arg);
            break;

        case CSL_VLYNQ_CMD_RAMS4_RXADRSIZE4_SET:
            /** Sets the Rx Address Map Size4 (RAMS4) register with a given
             *  address/value used in calculating the inbound
             *  packet address */
           CSL_vlynqRxAddrSize4Set (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_RAMO4_RXADROFFSET4_SET:
            /** Sets the Rx Address Map Offset4 (RAMO4) register with a
             *  given address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrOffset4Set (hVlynq, (CSL_VlynqAdrPtr)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC0_INT_ENA:
            /** Enable INTVEC0 (3-0) interrupt(s) */
            CSL_vlynqIntvec0Enable (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT_DIS:
            /** Disable INTVEC0 (3-0) interrupt(s) */
            CSL_vlynqIntvec0Disable (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC0_INT3_TYPE_SET:
            /** INTVEC0s' Interrupt-3 type */
            CSL_vlynqInt3TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT3_POL_SET:
            /** INTVEC0s' Interrupt-3 polarity */
            CSL_vlynqInt3PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT3_INTVEC_SET:
            /** INTVEC0's Interrupt-3 interrupt vector */
            CSL_vlynqInt3IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC0_INT2_TYPE_SET:
            /** INTVEC0s' Interrupt-2 type */
            CSL_vlynqInt2TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT2_POL_SET:
            /** INTVEC0s' Interrupt-2 polarity */
            CSL_vlynqInt2PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT2_INTVEC_SET:
            /** INTVEC0's Interrupt-2 interrupt vector */
            CSL_vlynqInt2IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC0_INT1_TYPE_SET:
            /** INTVEC0s' Interrupt-1 type */
            CSL_vlynqInt1TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT1_POL_SET:
            /** INTVEC0s' Interrupt-1 polarity */
            CSL_vlynqInt1PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT1_INTVEC_SET:
            /** INTVEC0's Interrupt-1 interrupt vector */
            CSL_vlynqInt1IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC0_INT0_TYPE_SET:
            /** INTVEC0s' Interrupt-0 type */
            CSL_vlynqInt0TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT0_POL_SET:
            /** INTVEC0s' Interrupt-0 polarity */
            CSL_vlynqInt0PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC0_INT0_INTVEC_SET:
            /** INTVEC0's Interrupt-0 interrupt vector */
            CSL_vlynqInt0IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC1_INT_ENA:
            /** Enable INTVEC1 (7-4) interrupt(s) */
            CSL_vlynqIntvec1Enable (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT_DIS:
            /** Disable INTVEC1 (7-4) interrupt(s) */
            CSL_vlynqIntvec1Disable (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC1_INT7_TYPE_SET:
            /** INTVEC1s' Interrupt-7 type */
            CSL_vlynqInt7TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT7_POL_SET:
            /** INTVEC1s' Interrupt-7 polarity */
            CSL_vlynqInt7PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT7_INTVEC_SET:
            /** INTVEC1's Interrupt-7 interrupt vector */
            CSL_vlynqInt7IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC1_INT6_TYPE_SET:
            /** INTVEC1s' Interrupt-6 type */
            CSL_vlynqInt6TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT6_POL_SET:
            /** INTVEC1s' Interrupt-6 polarity */
            CSL_vlynqInt6PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT6_INTVEC_SET:
            /** INTVEC1's Interrupt-6 interrupt vector */
            CSL_vlynqInt6IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC1_INT5_TYPE_SET:
            /** INTVEC1s' Interrupt-5 type */
            CSL_vlynqInt5TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT5_POL_SET:
            /** INTVEC1s' Interrupt-5 polarity */
            CSL_vlynqInt5PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT5_INTVEC_SET:
            /** INTVEC1's Interrupt-5 interrupt vector */
            CSL_vlynqInt5IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INTVEC1_INT4_TYPE_SET:
            /** INTVEC1s' Interrupt-4 type */
            CSL_vlynqInt4TypeSet (hVlynq, *(CSL_VlynqIntType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT4_POL_SET:
            /** INTVEC1s' Interrupt-4 polarity */
            CSL_vlynqInt4PolSet (hVlynq, *(CSL_VlynqIntPolType*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC1_INT4_INTVEC_SET:
            /** INTVEC1's Interrupt-4 interrupt vector */
            CSL_vlynqInt4IntvecSet (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

/** Commands for remote VLYNQs' configuration register */

        case CSL_VLYNQ_CMD_REMOTE_PMEN_DIS:
            /** Disable remote VLYNQ Power Management */
        case CSL_VLYNQ_CMD_REMOTE_PMEN_ENA:
            /** Enable remote VLYNQ Power Management */
            CSL_vlynqRemPmenConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_SCLKPUDIS_ENA:
            /** Enable remote VLYNQ Serial Clock Pull-up-disable */
        case CSL_VLYNQ_CMD_REMOTE_SCLKPUDIS_DIS:
            /** Disable remote VLYNQ Serial Clock Pull-up-disable */
            CSL_vlynqRemSclkpudisConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_RXSAMPLEVAL_SET:
            /** Set remote VLYNQ's RTM sample value */
            /* Razak: Added for simultaneous write to rxsampleval and
             * rtmvalidwr fields */
            CSL_vlynqRemSetRxSampleVal (hVlynq, *(CSL_VlynqRtmSampleVal*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_RTMVALIDWR_ENA:
            /** Enable remote VLYNQs' RTM Write valid */
        case CSL_VLYNQ_CMD_REMOTE_RTMVALIDWR_DIS:
            /** Disable remote VLYNQ RTM Write valid
             *  (rxsample val will be invalid) */
            CSL_vlynqRemRtmValidWrConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_RTMENABLE_ENA:
            /** Enable remote VLYNQs' RTM (Receive Timing Manager) */
        case CSL_VLYNQ_CMD_REMOTE_RTMENABLE_DIS:
            /** Disable remote VLYNQs' RTM (Receive Timing Manager) */
            CSL_vlynqRemRtmConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_TXFASTPATH_ENA:
            /** Selects remote VLYNQs' TX fast path */
        case CSL_VLYNQ_CMD_REMOTE_TXFASTPATH_DIS:
            /** Selects remote VLYNQs' TX Slow path */
            CSL_vlynqRemTxFastPathConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_CLKDIV_SET:
            /* Selects remote VLYNQs' Serial Clock divider value */
            CSL_vlynqRemClkDivSet (hVlynq, *(CSL_VlynqSclkDiv *)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_CLKDIR_INPUT:
            /** Remote VLYNQ clock is sourced externally */
        case CSL_VLYNQ_CMD_REMOTE_CLKDIR_OUTPUT:
            /** Remote VLYNQ uses internal clock,
             *  divided down vesrion of vlynk_clk_ref */
            CSL_vlynqRemClkDirSet (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_INTLOCAL_REMOTE:
            /** In remote VLYNQ, forward/transmit Interrupt packets
             *  over serial-interface */
        case CSL_VLYNQ_CMD_REMOTE_INTLOCAL_LOCAL:
            /** In remote VLYNQ, post Interrupts locally */
            CSL_vlynqRemIntLocalConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_INTENABLE_DIS:
            /** Disables remote VLYNQs' Status Interrupts */
        case CSL_VLYNQ_CMD_REMOTE_INTENABLE_ENA:
            /* Enables remote VLYNQs' Status Interrupts */
            CSL_vlynqRemIntEnConfigure (hVlynq, *(Uint32*)arg);
            break;

        /*Razak: added following 2 commands for setting & clearing
         * remote VLYNQs' intvec field */
        case CSL_VLYNQ_CMD_REMOTE_INTVEC_SET:
            /* Sets remote VLYNQs' intvec field */
            CSL_vlynqRemIntVecConfigure (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;
        case CSL_VLYNQ_CMD_REMOTE_INTVEC_CLR:
            /* Clears remote VLYNQs' intvec field */
            CSL_vlynqRemIntVecClear (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_INT2CFG_DIS:
            /** Disable remote VLYNQs' intcfg: Use INTPTR register
             *  as a pointer to memory */
        case CSL_VLYNQ_CMD_REMOTE_INT2CFG_ENA:
            /** Enable remote VLYNQs' intcfg: Use INTPTR register
             *  as a pointer to Configuration register */
            CSL_vlynqRemInt2CfgConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_AOPTDISABLE_ENA:
            /** Enable remote VLYNQs' Address Optimization */
        case CSL_VLYNQ_CMD_REMOTE_AOPTDISABLE_DIS:
            /** Disable remote VLYNQs' Address Optimization */
            CSL_vlynqRemAoptDisableConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_REMOTE_ILOOP_DIS:
            /** Disable remote VLYNQs' internal loop-back */
        case CSL_VLYNQ_CMD_REMOTE_ILOOP_ENA: