csl_vlynqhwcontrol.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/* ---- File: <csl_vlynqHwControl.c> ---- */

/** \file csl_vlynqHwControl.c
 *
 *  \brief    File for functional layer of CSL API \a CSL_vlynqHwControl()
 *
 *  Description
 *    - The \a CSL_vlynqHwControl() function definition & it's associated
 *      functions
 *
 */

/* ============================================================================
 *  Revision History
 *  ===============
 *  20-Dec-2004 Nsr Updated the source csl_vlynqHwControl.c for the new CSL
 *                  format.
 *
 * ============================================================================
 */

#include <csl_vlynq.h>
#include <csl_vlynqAux.h>

/** Takes a command with an optional argument & implements it. This function is
 * used to carry out the different operations performed by VLYNQ.
 *
 * @return returns the status of the operation
 *
 */
#pragma CODE_SECTION (CSL_vlynqHwControl, ".text:csl_section:vlynq");
CSL_Status  CSL_vlynqHwControl(
    /** pointer to the object that holds reference to the
     * instance of VLYNQ requested after the call */
    CSL_VlynqHandle                         hVlynq,
    /** the command to this API which indicates the action to be taken */
    CSL_VlynqHwControlCmd                   cmd,
    /** an optional argument @a void* casted */
    void                                    *arg
)
{

    CSL_Status status = CSL_SOK;

    switch (cmd){
    /** Commands for local VLYNQs' configuration register */

        case CSL_VLYNQ_CMD_PMEN_ENA:
            /** Enable Power Management */
        case CSL_VLYNQ_CMD_PMEN_DIS:
            /** Disable Power Management */
            CSL_vlynqPmenConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_SCLKPUDIS_DIS:
            /** Serial Clock Pull-up Disable */
        case CSL_VLYNQ_CMD_SCLKPUDIS_ENA:
            /** Serial Clock Pull-up Enable */
            CSL_vlynqSclkpudisConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_RXSAMPLEVAL_SET:
            /** Set RTM sample value */
            CSL_vlynqSetRxSampleVal (hVlynq, *(CSL_VlynqRtmSampleVal*)arg);
            break;

        case CSL_VLYNQ_CMD_RTMVALIDWR_DIS:
            /** Disable the RTM Write valid
             *  (rxsample val will be invalid) */
        case CSL_VLYNQ_CMD_RTMVALIDWR_ENA:
            /** Enable RTM Write valid -odd:7*/
            CSL_vlynqRtmValidWrConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_RTMENABLE_DIS:
            /** Disable RTM (Receive Timing Manager) */
        case CSL_VLYNQ_CMD_RTMENABLE_ENA:
            /** Enable RTM (Receive Timing Manager) */
            CSL_vlynqRtmConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_TXFASTPATH_DIS:
            /** Selects TX Slow path */
        case CSL_VLYNQ_CMD_TXFASTPATH_ENA:
            /** Selects TX fast path */
            CSL_vlynqTxFastPathConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_CLKDIV_SET:
            /* Selects Serial Clock divider value */
            CSL_vlynqClkDivSet (hVlynq, *(CSL_VlynqSclkDiv *)arg);
            break;

        case CSL_VLYNQ_CMD_CLKDIR_OUTPUT:
            /* VLYNQ uses internal clock, divided down
             *  vesrion of vlynk_clk_ref */
        case CSL_VLYNQ_CMD_CLKDIR_INPUT:
            /** VLYNQ clock is sourced externally */
            CSL_vlynqClkDirSet (hVlynq, *(CSL_VlynqClkDir*)arg);
            break;

        case CSL_VLYNQ_CMD_INTLOCAL_LOCAL:
            /** Post Interrupts locally -odd:15*/
        case CSL_VLYNQ_CMD_INTLOCAL_REMOTE:
            /* Forward/Transmit Interrupt packets over serial- interface */
            CSL_vlynqIntLocalConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_INTENABLE_ENA:
            /** Enables Status Interrupts -odd:17*/
        case CSL_VLYNQ_CMD_INTENABLE_DIS:
            /* Disables Status Interrupts */
            CSL_vlynqIntEnConfigure (hVlynq, *(Uint32*)arg);
            break;

        /*Razak: added following 2 commands for setting & clearing
         * intvec field */
        case CSL_VLYNQ_CMD_INTVEC_SET:
            /* Sets intvec field */
            CSL_vlynqIntVecConfigure (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;
        case CSL_VLYNQ_CMD_INTVEC_CLR:
            /* Clears intvec field*/
            CSL_vlynqIntVecClear (hVlynq, *(CSL_VlynqIntVector*)arg);
            break;

        case CSL_VLYNQ_CMD_INT2CFG_ENA:
            /** Use INTPTR register as a pointer to Configuration
             *  register */
        case CSL_VLYNQ_CMD_INT2CFG_DIS:
            /* Use INTPTR register as a pointer to memory */
            CSL_vlynqInt2CfgConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_AOPTDISABLE_DIS:
            /** Disable Address Optimization */
        case CSL_VLYNQ_CMD_AOPTDISABLE_ENA:
            /** Enable Address Optimization */
            CSL_vlynqAoptConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_ILOOP_ENA:
            /** Enable internal loop-back */
        case CSL_VLYNQ_CMD_ILOOP_DIS:
            /* Disable internal loop-back */
            CSL_vlynqILoopConfigure (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_SOFTRESET_ASSERT:
            /** Soft RESET:Assert soft reset */
        case CSL_VLYNQ_CMD_SOFTRESET_DEASSERT:
            /** Soft RESET:Deassert soft reset */
            CSL_vlynqSoftResetAssert (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_RERROR_CLR:
            /** Clear remote error status flag
             *  (This is write-1-to-clear filed) */
            CSL_vlynqRErrorClear (hVlynq);
            break;
        case CSL_VLYNQ_CMD_LERROR_CLR:
            /** Clear local error status flag
             *  (This is write-1-to-clear filed) */
             CSL_vlynqLErrorClear (hVlynq);
            break;

        case CSL_VLYNQ_CMD_INTPRI_INTSTAT_CLR:
            /** Clears the interrupt status (which has got highest priority)
             *  pending from the INTSTATCLR register */
             CSL_vlynqPriIntrStatClear (hVlynq);
            break;

        case CSL_VLYNQ_CMD_INTSTATCLR_INTCLR_CLR:
            /** Clear interrupt(s) status bits (refers to INTSTATCLR)
             *  (This is write-1-to-clear filed) */
            CSL_vlynqIntrStatClear (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_INTPENDSET_INTSET_SET:
            /* Sets/generates interrupt (refers to INTPENDSET register) */
            CSL_vlynqIntrPendSet (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_INTPENDSET_INTSET_CLR:
            /* Clear pending interrupts from INTPENDSET register */
            CSL_vlynqIntrPendSetClr (hVlynq, *(Uint32*)arg);
            break;

        case CSL_VLYNQ_CMD_INTPTR_REGPTR:
            /** Sets the INTPTR to point a configuration register */
        case CSL_VLYNQ_CMD_INTPTR_MEMPTR:
            /* Sets the INTPTR to point to memory */
            CSL_vlynqIntrPtrSet (hVlynq, (CSL_VlynqAdrPtr)arg);
            break;

        case CSL_VLYNQ_CMD_XAM_TXADRMAP_SET:
            /** Sets the Tx Address Map (XAM) register with a given
             *  address/value used in translating the transmit
             *  packet address */
            CSL_vlynqTxAddrMapSet (hVlynq, (CSL_VlynqAdrPtr)arg);
            break;

        case CSL_VLYNQ_CMD_RAMS1_RXADRSIZE1_SET:
            /** Sets the Rx Address Map Size1 (RAMS1) register with a given
             *  address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrSize1Set (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_RAMO1_RXADROFFSET1_SET:
            /** Sets the Rx Address Map Offset1 (RAMO1) register with a
             *  given address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrOffset1Set (hVlynq, (CSL_VlynqAdrPtr)arg);
            break;

        case CSL_VLYNQ_CMD_RAMS2_RXADRSIZE2_SET:
            /** Sets the Rx Address Map Size2 (RAMS2) register with a given
             *  address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrSize2Set (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_RAMO2_RXADROFFSET2_SET:
            /** Sets the Rx Address Map Offset2 (RAMO2) register with a
             *  given address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrOffset2Set (hVlynq, (CSL_VlynqAdrPtr)arg);
            break;

        case CSL_VLYNQ_CMD_RAMS3_RXADRSIZE3_SET:
            /** Sets the Rx Address Map Size3 (RAMS3) register with a given
             *  address/value used in calculating the inbound
             *  packet address */
            CSL_vlynqRxAddrSize1Set (hVlynq, *(Uint32*)arg);
            break;
        case CSL_VLYNQ_CMD_RAMO3_RXADROFFSET3_SET:
            /** Sets the Rx Address Map Offset3 (RAMO3) register with a