csl_tmrhwsetup.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *   ===========================================================================
 */

/** @file csl_tmrHwSetup.c
 *
 *  @brief    File for functional layer of CSL API @a CSL_tmrHwSetup()
 *
 *  Description
 *    - The @a CSL_tmrHwSetup() function definition & it's associated
 *      functions
 *
 *  Path: \\(CSLPATH)\\ipmodules\\timer\\src
 */

/* =============================================================================
 *  Revision History
 *  ===============
 *  1-Sept-2004 HMM File Created.
 * =============================================================================
 */

#include <csl_tmr.h>

/** ============================================================================
 *   @n@b CSL_tmrHwSetup
 *
 *   @b Description
 *   @n It configures the tmr registers as per the values passed
 *      in the hardware setup structure.
 *
 *   @b Arguments
 *   @verbatim
            hTmr            Handle to the TMR instance
            hwSetup         Pointer to harware setup structure
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Hardware setup successful.
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *   @li                    CSL_ESYS_INVPARAMS  - Hardware structure is not
                                                  properly initialized
 *
 *   @b Modifies
 *   @n The hardware registers of TMR.
 *
 *   @b Example
 *   @verbatim
        CSL_TmrHandle    hTmr;
        CSL_TmrObj       tmrObj;
        CSL_TmrHwSetup   hwSetup;
        CSL_status       status;

        ...

        hTmr = CSL_tmrOpen (&tmrObj, CSL_TMR_PRIMARY, NULL, &status);

        status = CSL_tmrHwSetup(hTmr, &hwSetup);
 *   @endverbatim
 *  ============================================================================
 */
#pragma CODE_SECTION (CSL_tmrHwSetup, ".text:csl_section:tmr");
CSL_Status CSL_tmrHwSetup (
    CSL_TmrHandle            hTmr,
    CSL_TmrHwSetup          *hwSetup
)
{
    if (hTmr == NULL) {
        return CSL_ESYS_BADHANDLE;
    }

    if (hwSetup == NULL) {
        return CSL_ESYS_INVPARAMS;
    }

    /* Setup GPINT_GPEN configuration */
    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT34_ENI,\
             hwSetup->tmrGpInt34Eni);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT34_ENO,\
             hwSetup->tmrGpInt34Eno);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT34_INVI,\
             hwSetup->tmrGpInt34Invi);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT34_INVO,\
             hwSetup->tmrGpInt34Invo);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT12_ENI,\
             hwSetup->tmrGpInt12Eni);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT12_ENO,\
             hwSetup->tmrGpInt12Eno);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT12_INVI,\
             hwSetup->tmrGpInt12Invi);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPINT12_INVO,\
             hwSetup->tmrGpInt12Invo);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPIO_ENI34,\
             hwSetup->tmrGpIoEni34);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPIO_ENO34,\
             hwSetup->tmrGpIoEno34);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPIO_ENI12,\
             hwSetup->tmrGpIoEni12);

    CSL_FINS(hTmr->regs->GPINT_GPEN, TMR_GPINT_GPEN_GPIO_ENO12,\
             hwSetup->tmrGpIoEno12);

    /* Setup GPTDAT_GPDIR configuration */
    CSL_FINS(hTmr->regs->GPTDAT_GPDIR, TMR_GPTDAT_GPDIR_GPIO_DIRO34,\
             hwSetup->tmrGpDirDiro34);

    CSL_FINS(hTmr->regs->GPTDAT_GPDIR, TMR_GPTDAT_GPDIR_GPIO_DIRI34,\
             hwSetup->tmrGpDirDiri34);

    CSL_FINS(hTmr->regs->GPTDAT_GPDIR, TMR_GPTDAT_GPDIR_GPIO_DIRO12,\
             hwSetup->tmrGpDirDiro12);

    CSL_FINS(hTmr->regs->GPTDAT_GPDIR, TMR_GPTDAT_GPDIR_GPIO_DIRI12,\
             hwSetup->tmrGpDirDiri12);

    /* Load the Period register's */
    hTmr->regs->PRD12 = hwSetup->tmrTimerPeriod12;
    hTmr->regs->PRD34 = hwSetup->tmrTimerPeriod34;

    /* Load the counter register's */
    hTmr->regs->TIM12 = hwSetup->tmrTimerCounter12;
    hTmr->regs->TIM34 = hwSetup->tmrTimerCounter34;

    /* Setup the TCR34 register configurations */
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_TIEN34,    hwSetup->tmrIpGate34);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_CLKSRC34,  hwSetup->tmrClksrc34);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_PWID34,    hwSetup->tmrPulseWidth34);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_CP34,      hwSetup->tmrClockPulse34);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVINP34,  hwSetup->tmrInvInp34);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVOUTP34, hwSetup->tmrInvOutp34);

    /* Setup the TCR12 register configurations */
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_TIEN12,    hwSetup->tmrIpGate12);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_CLKSRC12,  hwSetup->tmrClksrc12);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_PWID12,    hwSetup->tmrPulseWidth12);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_CP12,      hwSetup->tmrClockPulse12);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVINP12,  hwSetup->tmrInvInp12);
    CSL_FINS(hTmr->regs->TCR, TMR_TCR_INVOUTP12, hwSetup->tmrInvOutp12);

    /* Setup the TGCR register  configurations */
    CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_PSC34, hwSetup->tmrPreScalarCounter34);

    /* check for the operation mode */
    if ((hwSetup->tmrTimerMode) != CSL_TMR_TIMMODE_WDT) {
        CSL_FINS(hTmr->regs->TGCR, TMR_TGCR_TIMMODE, hwSetup->tmrTimerMode);
    }
    else {
        return CSL_ESYS_INVPARAMS;
    }

    return CSL_SOK;
}