csl_nandgethwsetup.c

TI达芬奇dm644x各硬件模块测试代码

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005                 
 *                                                                              
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.             
 *   ===========================================================================
 */ 

/** @file csl_nandGetHwSetup.c
 *
 *    @brief    File for functional layer of CSL API @a CSL_nandGetHwSetup()
 *
 *  Description
 *    - The @a CSL_nandGetHwSetup() function definition & it's associated
 *      functions
 *  Path: \\(CSLPATH)\\ipmodules\\nfc\\src
 *
 *  Modification 1
 *    - Modified on: 28/6/2004
 *    - Reason: created the sources
 *
 *  @date 28th June, 2004
 *  @author Santosh Narayanan.
 */

#include <csl_nand.h>

/** ============================================================================
 *   @n@b CSL_NandGetHwSetup
 *
 *   @b Description
 *   @n Gets the current setup of NAND.
 *
 *   @b Arguments
 *   @verbatim
            hNand           Handle to the NAND instance

            setup           Pointer to setup structure which contains the
                            setup information of NAND.
     @endverbatim
 *
 *   <b> Return Value </b>  CSL_Status
 *   @li                    CSL_SOK             - Setup info load successful.
 *   @li                    CSL_ESYS_BADHANDLE  - Invalid handle
 *   @li                    CSL_ESYS_INVPARAMS  - Invalid parameter
 *
 *   <b> Pre Condition </b>
 *   @n  None
 *
 *   <b> Post Condition </b>
 *   @n  The registers of the specified NAND instance will be setup.
 *
 *   @b Modifies
 *   @n Hardware registers of the specified NAND instance.
 *
 *   @b Example
 *   @verbatim
        CSL_NandHandle       hNand;
        CSL_NandHwSetup      setup;
        CSL_Status           status;

        status = CSL_NandGetHwSetup (hNand, &setup);
     @endverbatim
 * =============================================================================
 */
#pragma CODE_SECTION (CSL_nandGetHwSetup, ".text:csl_section:nand")
CSL_Status  CSL_nandGetHwSetup(
    /** Pointer to the object that holds reference to the
     *  instance of NAND requested after the call 
     */
    CSL_NandHandle                         hNand,
    /** Pointer to setup structure which contains the
     *  information to program NAND to a useful state 
     */
    CSL_NandHwSetup                        *setup
)
{
    CSL_Status status = CSL_SOK;

      /* Get the Async Bank 1 setup */      
    setup->asyncBank1Config->selectStrobe 
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_SS);
    setup->asyncBank1Config->extWait
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_EW);
    setup->asyncBank1Config->writeSetup 
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_W_SETUP);
    setup->asyncBank1Config->writeStrobe 
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_W_STROBE);
    setup->asyncBank1Config->writeHold 
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_W_HOLD);
    setup->asyncBank1Config->readSetup 
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_R_SETUP);
    setup->asyncBank1Config->readStrobe
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_R_STROBE);
    setup->asyncBank1Config->readHold
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_R_HOLD);
    setup->asyncBank1Config->turnAround
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_TA);
    setup->asyncBank1Config->asyncSize 
                              = CSL_FEXT(hNand->regs->AB1CR, NAND_AB1CR_ASIZE);
       
      /* Get the Async Bank 2 setup */      
    setup->asyncBank2Config->selectStrobe
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_SS);
    setup->asyncBank2Config->extWait 
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_EW);
    setup->asyncBank2Config->writeSetup 
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_W_SETUP);
    setup->asyncBank2Config->writeStrobe 
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_W_STROBE);
    setup->asyncBank2Config->writeHold 
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_W_HOLD);
    setup->asyncBank2Config->readSetup
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_R_SETUP);
    setup->asyncBank2Config->readStrobe 
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_R_STROBE);
    setup->asyncBank2Config->readHold
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_R_HOLD);
    setup->asyncBank2Config->turnAround
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_TA);
    setup->asyncBank2Config->asyncSize
                           = CSL_FEXT(hNand->regs->AB2CR, NAND_AB2CR_ASIZE);
    
      /* Get the Async Bank 3 setup */      
    setup->asyncBank3Config->selectStrobe
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_SS);
    setup->asyncBank3Config->extWait 
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_EW);
    setup->asyncBank3Config->writeSetup
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_W_SETUP);
    setup->asyncBank3Config->writeStrobe 
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_W_STROBE);
    setup->asyncBank3Config->writeHold
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_W_HOLD);
    setup->asyncBank3Config->readSetup
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_R_SETUP);
    setup->asyncBank3Config->readStrobe
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_R_STROBE);
    setup->asyncBank3Config->readHold 
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_R_HOLD);
    setup->asyncBank3Config->turnAround
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_TA);
    setup->asyncBank3Config->asyncSize
                          = CSL_FEXT(hNand->regs->AB3CR, NAND_AB3CR_ASIZE);
       
      /* Get the Async Bank 4 setup */      
    setup->asyncBank4Config->selectStrobe
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_SS);
    setup->asyncBank4Config->extWait
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_EW);
    setup->asyncBank4Config->writeSetup 
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_W_SETUP);
    setup->asyncBank4Config->writeStrobe 
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_W_STROBE);
    setup->asyncBank4Config->writeHold
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_W_HOLD);
    setup->asyncBank4Config->readSetup
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_R_SETUP);
    setup->asyncBank4Config->readStrobe
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_R_STROBE);
    setup->asyncBank4Config->readHold 
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_R_HOLD);
    setup->asyncBank4Config->turnAround
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_TA);
    setup->asyncBank4Config->asyncSize
                          = CSL_FEXT(hNand->regs->AB4CR, NAND_AB4CR_ASIZE);
    
       /* Get the Async Wait Cycle Configuration */
    setup->asyncWaitCycleConfig->wp3 
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_WP3);
    setup->asyncWaitCycleConfig->wp2 
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_WP2);
    setup->asyncWaitCycleConfig->wp1
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_WP1);
    setup->asyncWaitCycleConfig->wp0 
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_WP0);
    setup->asyncWaitCycleConfig->cs3Wait 
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_CS3WAIT);
    setup->asyncWaitCycleConfig->cs2Wait
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_CS2WAIT);   
    setup->asyncWaitCycleConfig->cs1Wait
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_CS1WAIT);
    setup->asyncWaitCycleConfig->cs0Wait
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_CS0WAIT);
    setup->asyncWaitCycleConfig->maxExtWait
                           = CSL_FEXT(hNand->regs->AWCCR, NAND_AWCCR_MEWC);   

    /* Get the NAND FLASH Control Configuration */ 
    setup->nandFlashControl->cs5nand 
                       = CSL_FEXT(hNand->regs->NANDFCR, NAND_NANDFCR_CS5NAND);
    setup->nandFlashControl->cs4nand 
                       = CSL_FEXT(hNand->regs->NANDFCR, NAND_NANDFCR_CS4NAND);
    setup->nandFlashControl->cs3nand
                       = CSL_FEXT(hNand->regs->NANDFCR, NAND_NANDFCR_CS3NAND);    
    setup->nandFlashControl->cs2nand
                       = CSL_FEXT(hNand->regs->NANDFCR, NAND_NANDFCR_CS2NAND);

    return status;
}